KR100199365B1 - Fabrication method of semiconductor device - Google Patents
Fabrication method of semiconductor device Download PDFInfo
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- KR100199365B1 KR100199365B1 KR1019960023457A KR19960023457A KR100199365B1 KR 100199365 B1 KR100199365 B1 KR 100199365B1 KR 1019960023457 A KR1019960023457 A KR 1019960023457A KR 19960023457 A KR19960023457 A KR 19960023457A KR 100199365 B1 KR100199365 B1 KR 100199365B1
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- Prior art keywords
- polysilicon layer
- oxide film
- film
- forming
- insulating film
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 239000004065 semiconductor Substances 0.000 title claims abstract description 7
- 238000000034 method Methods 0.000 title claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 41
- 229920005591 polysilicon Polymers 0.000 claims abstract description 41
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 11
- 229920002120 photoresistant polymer Polymers 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 8
- 230000010354 integration Effects 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
본 발명은 반도체 소자의 제조방법을 제공하는 것으로, 필드산화막 상에서 제1폴리실리콘층 패턴시 제1폴리실리콘층이 필드산화막과 많이 중첩되게하여 플로팅 게이트 및 컨트롤 게이트간 접촉면적을 증가시키므로써 패캐시터의 커플림비를 크게하여 낮은 구동전압에서도 안정적으로 소자가 동작하게 되고, 이는 챠지펌프 회로를 작게 형성하므로서 고집적화를 실현할 수 있는 효과가 있다.The present invention provides a method of manufacturing a semiconductor device, wherein a first polysilicon layer on a field oxide film is overlaid with a first polysilicon layer a lot with a field oxide film to increase the contact area between the floating gate and the control gate, And the device operates stably even at a low driving voltage. This makes it possible to achieve high integration by forming a small charge pump circuit.
Description
제1도는 일반적인 플래쉬 메모리셀의 레이아웃도.FIG. 1 is a layout diagram of a general flash memory cell. FIG.
제2a도는 제1도의 A1 - A2선을 따라 절취한 소자의 단면도.Figure 2a is a cross-sectional view of the element taken along the line A1-A2 of Figure 1;
제2b도는 제1도의 B1 - B2선을 따라 절취한 소자의 단면도.2b is a cross-sectional view of the element taken along line B1-B2 of FIG. 1;
제3도는 본 발명에 따른 플래쉬 메모리셀의 레이아웃도.FIG. 3 is a layout diagram of a flash memory cell according to the present invention; FIG.
제4a 내지 4e도는 본 발명의 플래쉬 메모리셀을 형성하는 단계를 설명하기 위해 제3도의 C1 - C2선을 따라 절취한 소자의 단면도.4a to 4e are cross-sectional views of the device taken along line C1-C2 of FIG. 3 to illustrate the step of forming the flash memory cell of the present invention.
제5a 내지 5f도는 본 발명의 플래쉬 메모리셀을 형성하는 단계를 설명하기 위해 제3도의 D1 - D2선을 따라 절취한 소자의 단면도.5a to 5f are cross-sectional views of the device taken along the line D1-D2 of FIG. 3 to illustrate the step of forming the flash memory cell of the present invention.
* 도면의 주요부분에 대한 부호의 설명DESCRIPTION OF THE REFERENCE NUMERALS
1, 11 : 실리콘기판 2, 12 : 필드산화막1, 11: silicon substrate 2, 12: field oxide film
3, 13 : 터널산화막 4, 14 : 제1폴리실리콘층(플로팅게이트)3, 13: tunnel oxide film 4, 14: first polysilicon layer (floating gate)
5, 15 : 유전체막 6, 16 : 제2폴리실리콘층(컨트롤 게이트)5, 15: dielectric film 6, 16: second polysilicon layer (control gate)
17 : 절연막 18 : 감광막 패턴17: insulating film 18: photosensitive film pattern
19 : 산화막 M2, M12 : 필드산화막 마스크19: oxide film M2, M12: field oxide film mask
M4, M14 : 제1폴리실리콘층 마스크 M6, M16 : 제2폴리실리콘층 마스크M4, M14: first polysilicon layer mask M6, M16: second polysilicon layer mask
본 발명은 반도체 소자의 제조방법에 관한 것으로 특히, 스플릿 게이트형 플래쉬 메모리 셀에 있어서, 플로팅 게이트 및 컨트롤 게이트간의 접촉면적을 증가시킬 수 있는 반도체 소자의 제조방법에 관한 것이다.More particularly, the present invention relates to a method of manufacturing a semiconductor device capable of increasing a contact area between a floating gate and a control gate in a split gate type flash memory cell.
일반적으로 스플릿 게이트(Split Gate)형 플래쉬 메모리 소자의 형성에 있어서, 플로팅 게이트, 유전체막 및 컨트롤 게이트로 이루어지는 적층형 게이트전극을 형성한 후 접합영역 및 절연막을 형성하고, 절연막을 선택 식각하여 채널을 형성시킨 후 셀렉트 게이트를 형성하게 되는데 그러면 종래 반도체 소자의 제조공정을 첨부된 도면을 참조하여 설명하면 다음과 같다.Generally, in the formation of a split gate type flash memory device, a lamination type gate electrode composed of a floating gate, a dielectric film and a control gate is formed and then a junction region and an insulating film are formed, and an insulating film is selectively etched to form a channel And then the select gate is formed. The conventional semiconductor device manufacturing process will now be described with reference to the accompanying drawings.
제1도는 일반적인 플래쉬 메모리셀의 레이아웃도이며, 제2a 및 2b도는 제1도의 A1 - A2 및 B1 - B2선을 따라 절취한 소자의 단면도이다.FIG. 1 is a layout view of a general flash memory cell, and FIGS. 2 (a) and 2 (b) are cross-sectional views of the device taken along lines A1-A2 and B1-B2 in FIG.
먼저 필드산화막가 마스크(M2)를 이용하여 실리콘기판(1)상에 필드산화막(2)을 형성한 후 터널산화막(3)을 형성한다. 그리고, 실리콘기판(1)의 전체 상부면에 제1폴리실리콘층(4)을 형성한 후 제1폴리실리콘층 마스크(M4)를 이용하여 패터닝한 후 실리콘기판(1)의 전체 상부면에 유전체막(5) 및 제2폴리실리콘층(6)을 순차적으로 형성한다. 그 후 제2폴리실리콘층 마스크(M6)를 이용하여 제2폴리실리콘층(6), 유전체막(5) 및 제1폴리실리콘층(4)을 패터닝한다. 이때 제1 및 제2폴리실리콘층(4 및 6)은 각각 플로팅 게이트 및 컨트롤 게이트가 된다. 그 다음 소스 드레인 마스크(도시안됨)를 이용하여 접합영역(10)을 형성한다.First, the field oxide film 2 is formed on the silicon substrate 1 by using the field oxide film mask M2, and then the tunnel oxide film 3 is formed. After the first polysilicon layer 4 is formed on the entire upper surface of the silicon substrate 1 and then patterned using the first polysilicon layer mask M4, A film 5 and a second polysilicon layer 6 are sequentially formed. The second polysilicon layer 6, the dielectric film 5 and the first polysilicon layer 4 are then patterned using a second polysilicon layer mask M6. Wherein the first and second polysilicon layers 4 and 6 are a floating gate and a control gate, respectively. The junction region 10 is then formed using a source drain mask (not shown).
이렇게하여 제2a도에 도시한 바와같이 필드산화막(2)상에 형성된 제1폴리실리콘층(4)은 필드산화막(2)의 가장자리에서 패터닝 했기 때문에 필드산화막(2) 중앙의 넓은 부분은 필요가 없게된다. 즉, 플로팅 게이트의 면적은 액티브 영역에 국한 되기 때문에 컨트롤 게이트와의 접촉면적은 작아지게 된다. 이에따라 플로팅 게이트의 끝부분에서 캐패시터 커플링의 손실이 발생되어 컨트롤 게이트의 동작전압은 커지게 되고, 이 동작전압을 크게하기 위해서는 챠지펌프 회로를 큰 면적에 형성해야 하는데 이는 결국 반도체 소자의 고집적화에 어려운 문제를 유발한다. 또한 프로그램과 소거시 고전압을 사용하게 되면 필드산화막(2)의 두께와 N채널 불소(F) 이온의 도즈량이 증가하기 때문에 액티브 및 필드간 단차가 심해져서 워드라인으로 사용되는 제3폴리실리콘층상에 형성되는 실리사이드의 나쁜 스텝 커버리지로 속도가 지연되고, 후속공정이 어렵게 되는 문제가 있다.2A, since the first polysilicon layer 4 formed on the field oxide film 2 is patterned at the edge of the field oxide film 2, a wide portion at the center of the field oxide film 2 is unnecessary I will not. That is, since the area of the floating gate is limited to the active region, the contact area with the control gate becomes small. Accordingly, a loss of capacitor coupling occurs at the end of the floating gate, so that the operating voltage of the control gate becomes large. In order to increase the operating voltage, the charge pump circuit must be formed in a large area. It causes problems. In addition, when a high voltage is used in programming and erasing, since the thickness of the field oxide film 2 and the dose amount of the N-channel fluorine (F) ion are increased, the active and field-to-field steps are worsened and the third polysilicon layer There is a problem that the speed is delayed due to the bad step coverage of the silicide to be formed and the subsequent process becomes difficult.
따라서 본 발명은 제1폴리실리콘층을 필드산화막상에서 많이 증첩되게하여 플로팅 게이트 및 컨트롤 게이트간 접촉면적을 증가시키므로써 상기 한 단점을 해소할 수 있는 반도체 소자의 제조방법을 제공하는 데 그 목적이 있다.SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a method of manufacturing a semiconductor device which can solve the above-described disadvantages by increasing the contact area between the floating gate and the control gate by causing the first polysilicon layer to be highly overlapped on the field oxide film .
상기한 목적을 달성하기 위한 본 발명의 소자 제조방법은 필드산화막이 형성된 실리콘기판상에 터널산화막을 형성한 후 실리콘기판의 전체 상부면에 제1폴리실리콘층 및 유전체막을 형성하는 단계와, 상기 단계로부터 유전체막상에 절연막을 형성한 후 그 위에 감광막 패턴을 형성하는 단계와, 상기 단계로부터 감광막 패턴을 마스크로 이용하여 유전체막이 노출되도록 절연막을 경사지게 식각한 후 감광막 패턴을 제거하는 단계와, 상기 단계로부터 절연막을 마스크로 이용하여 유전체막 및 제1폴리실리콘층을 소정싶이 식각한 후 절연막을 제거하는 단계와, 상기 단계로부터 산화공정으로 소정깊이 식각된 제1폴리실리콘층의 공간이 메워지도록 산화막을 형성한 후 실리콘기판의 전체 상부면에 제2폴리실리콘층을 형성하는 단계와, 상기 단계로부터 제2폴리실리콘층, 유전체막 및 제1폴리실리콘층을 자기정합식각방법으로 식각하는 단계로 이루어지는 것을 특징으로 한다.According to another aspect of the present invention, there is provided a method of fabricating a device, comprising: forming a tunnel oxide film on a silicon substrate having a field oxide film formed thereon; forming a first polysilicon layer and a dielectric film on the entire upper surface of the silicon substrate; Forming a dielectric film on the dielectric film and forming a photoresist pattern on the dielectric film, removing the photoresist pattern from the dielectric film by obliquely etching the dielectric film to expose the dielectric film using the photoresist pattern as a mask, Etching the dielectric film and the first polysilicon layer using an insulating film as a mask and then removing the insulating film; and forming an oxide film on the first polysilicon layer so as to fill the space of the first polysilicon layer, Forming a second polysilicon layer on the entire upper surface of the silicon substrate after formation; Etching the second polysilicon layer, the dielectric film, and the first polysilicon layer by a self-aligned etching method.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제3도는 본 발명에 따른 플래쉬 메모리셀의 레이아웃도이며, 제4a 내지 4e도는 플래쉬 메모리셀을 형성하는 단계를 설명하기 위해 제3도의 C1 - C2선을 따라 절취한 소자의 단면도이고, 제5a 내지 5f도는 플래쉬 메모리셀을 형성하는 단계를 설명하기 위해 제3도의 D1 - D2선을 따라 절취한 소자의 단면도이다.FIG. 3 is a layout view of a flash memory cell according to the present invention. FIGS. 4a to 4e are cross-sectional views of a device taken along line C1-C2 of FIG. 3 to explain a step of forming a flash memory cell, 5f is a cross-sectional view of the device taken along line D1-D2 of FIG. 3 to illustrate the step of forming a flash memory cell.
제4a 및 5a도는 필드산화막 마스크(M12)를 이용하여 실리콘기판(11)상에 필드산화막(12)을 형성한 후 터널산화막(13)을 형성하고, 실리콘기판(11)의 전체 상부면에 제1폴리실리콘층(14) 및 유전체막(15)을 형성한 상태를 도시한다.The field oxide film 12 is formed on the silicon substrate 11 using the field oxide film mask M12 shown in FIGS. 4A and 5A and the tunnel oxide film 13 is formed on the entire upper surface of the silicon substrate 11. Then, 1 polysilicon layer 14 and the dielectric film 15 are formed.
제4b도 및 5b도는 유전체막(15)상에 절연막(17)을 형성한 후 그 위에 제1폴리실리콘층 마스크(M14)를 이용하여 감광막 패턴(18)을 형성한 상태를 도시한다. 절연막(17)은 중간온도 산화막을 사용한다.4b and 5b show a state in which the insulating film 17 is formed on the dielectric film 15 and the photosensitive film pattern 18 is formed thereon using the first polysilicon layer mask M14. The insulating film 17 uses an intermediate-temperature oxide film.
제4c도 및 5c도는 감광막 패턴(18)을 마스크로 이용하여 유전체막(15)이 노출되도록 절연막(17)을 경사지게 식각한 후 감광막 패턴(18)을 제거한 상태를 도시한다. 즉, 절연막(17)이 경사지게 식각되므로써 노출되는 유전체막(15)의 면적은 감광막 패턴(18)의 개방된 부분보다 매우 좁아지게 된다.4c and 5c show a state in which the photoresist pattern 18 is removed after the insulating film 17 is obliquely etched to expose the dielectric film 15 using the photoresist pattern 18 as a mask. That is, since the insulating film 17 is obliquely etched, the exposed area of the dielectric film 15 becomes much narrower than the open portion of the photoresist pattern 18.
제4d도 및 5d도는 절연막(17)을 마스크로 이용하여 유전체막(15) 및 제1폴리실리콘층(14)을 소정깊이 식각한 후 절연막(17)을 제거한 상태를 도시한다.4d and 5d show a state in which the insulating film 17 is removed after the dielectric film 15 and the first polysilicon layer 14 are etched to a predetermined depth using the insulating film 17 as a mask.
제4e도 및 5e도는 산화공정으로 소정깊이 식각된 제1폴리실리콘층(14)의 공간이 메워지도록 산화막(19)을 형성한 후 실리콘기판(11)의 전체 상부면에 제2폴리실리콘층(16)을 형성한 상태를 도시한다.4e and 5e show an oxide film 19 formed so as to fill the space of the first polysilicon layer 14 which is etched to a predetermined depth by the oxidation process and then a second polysilicon layer 16 are formed.
제5f도는 제2폴리실리콘층 마스크(M16)를 이용하여 제2폴리실리콘층(16), 유전체막(15) 및 제1폴리실리콘층(14)를 자기정합 식각한 상태를 도시한다. 이렇게하여 제1폴리실리콘층(14)은 플로팅 게이트가 되고, 제2폴리실리콘층(16)은 컨트롤 게이트가 된다.5f shows a state in which the second polysilicon layer 16, the dielectric film 15 and the first polysilicon layer 14 are self-aligned etched using the second polysilicon layer mask M16. Thus, the first polysilicon layer 14 becomes a floating gate and the second polysilicon layer 16 becomes a control gate.
상술한 바와같이 본 발명에 의하면 필드산화막 상에서 제1폴리실리콘층 패턴시 제1폴리실리콘층이 필드산화막과 많이 중첩되게하여 플로팅 게이트 및 컨트롤 게이트 간 접촉면적을 증가시키므로써 패캐시터의 커플링비를 크게하여 낮은 구동전압에서도 안정적으로 소자가 동작하게 되고, 이는 챠지펌프 회로를 작게 형성하므로서 고집적화를 실현할 수 있는 탁월한 효과가 있다.As described above, according to the present invention, since the first polysilicon layer overlaps the field oxide film in the first polysilicon layer pattern on the field oxide film, the contact area between the floating gate and the control gate is increased, So that the device operates stably even at a low driving voltage. This makes it possible to achieve high integration by forming the charge pump circuit small.
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