KR980005879A - How to Form a Thin Film Transistor - Google Patents

How to Form a Thin Film Transistor Download PDF

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Publication number
KR980005879A
KR980005879A KR1019960023636A KR19960023636A KR980005879A KR 980005879 A KR980005879 A KR 980005879A KR 1019960023636 A KR1019960023636 A KR 1019960023636A KR 19960023636 A KR19960023636 A KR 19960023636A KR 980005879 A KR980005879 A KR 980005879A
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KR
South Korea
Prior art keywords
bottom gate
forming
gate electrode
thin film
film transistor
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Application number
KR1019960023636A
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Korean (ko)
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KR100201781B1 (en
Inventor
최국선
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김주용
현대전자산업 주식회사
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Priority to KR1019960023636A priority Critical patent/KR100201781B1/en
Publication of KR980005879A publication Critical patent/KR980005879A/en
Application granted granted Critical
Publication of KR100201781B1 publication Critical patent/KR100201781B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)

Abstract

본 발명은 바텀 게이트형 박막 트랜지스터 제조방법에 있어서, 폴리실리콘막을 패터닝하여 바텀 게이트 전극을 형상하는 제1단계, 상기 바텀 게이트 전극의 모서리 부분의 게이트 산화막을 두껍게 증착하기 위하여 상기 바컴 게이트 전극의 탑모서리를 소정부분 비정질화하는 제2단계, 게이트 산화막을 형성하는 제3단계를 포함하여 이루어지는 것을 특징으로 한다.In the method of manufacturing a bottom gate type thin film transistor, a first step of forming a bottom gate electrode by patterning a polysilicon layer, and a top edge of the bottom gate electrode to thickly deposit a gate oxide film of an edge portion of the bottom gate electrode And a third step of amorphizing a predetermined portion, and a third step of forming a gate oxide film.

Description

박막 트랜지스터 형성 방법How to Form a Thin Film Transistor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도 내지 제3도는 본 발명의 일실시예에 따른 박막 트랜지스터 제조 공정도이다.1 to 3 are process charts of manufacturing a thin film transistor according to an embodiment of the present invention.

Claims (5)

바텀 게이트형 박막 트랜지스터 제조방법에 있어서, 폴리 실리콘막을 패터닝하여 바텀 게이트 전극을 형성하는 제1단계, 상기 바텀 게이트 전극의 모서리 부분의 게이트 산화막을 두껍게 증착하기 위하여 상기 바텀 게이트 전극의 탑 모서리를 소정부분 비정질화 하는 제2단계, 게이트 산화막을 형성하는 제3단계를 포함하여 이루어지는 것을 특징으로 하는바텀 게이트형 박막트랜지스터 제조방법.A method of manufacturing a bottom gate type thin film transistor, the method comprising: forming a bottom gate electrode by patterning a polysilicon layer; and forming a top edge of the bottom gate electrode to thickly deposit a gate oxide film of an edge portion of the bottom gate electrode. A bottom gate type thin film transistor manufacturing method comprising a second step of amorphous, and a third step of forming a gate oxide film. 제1항에 있어서, 상기 제2단계는 상기 제1단계에서 사용된 감광막 패턴의 바텀 게이트 전극 모서리 소정부위를 제거한 후, 산화막 건식 식각 공정을 하여 이루어지는 것을 특징으로 하는 바텀 게이트형 박막 트랜지스터 제조방법.The method of claim 1, wherein the second step is performed by performing an oxide dry etching process after removing a predetermined portion of a bottom gate electrode corner of the photoresist pattern used in the first step. 제1항에 있어서, 상기 제2단계는 상기 제1단계에서 사용된 감광막 패턴의 바텀 게이트 전극 모서리 소정부위를 제거한 후, 이온주입 공정을 하여 이루어지는 것을 특징으로 하는 바텀 제이트형 박막 트랜지스터 제조방법.2. The method of claim 1, wherein the second step is performed by removing a predetermined portion of the bottom gate electrode edge of the photoresist pattern used in the first step, and then performing an ion implantation process. 제1항에 있어서, 상기 제3단계는 전체구조 상부에 열산화 공정으로 게이트 산화막을 형성하는 단계인 것을 특징으로 하는 바텀 게이트형 박막 트랜지스터 제조방법.The method of claim 1, wherein the third step is a step of forming a gate oxide layer on the entire structure by a thermal oxidation process. 제1항에 있어서, 상기 제3단계는 전체구조 상부에 열산화 공정으로 소정 두께의 게이트 산화막을 형성하고 CVD공정으로 나머지 두께의 게이트 산화막을 증착하는 단계인 것을 특징으로 하는 바텀 게이트형 박막 트랜지스터 제조방법.The bottom gate type thin film transistor according to claim 1, wherein the third step is a step of forming a gate oxide film having a predetermined thickness on the entire structure by a thermal oxidation process and depositing a gate oxide film having a remaining thickness by a CVD process. Way. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019960023636A 1996-06-25 1996-06-25 Method of forming thin film transistor KR100201781B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960023636A KR100201781B1 (en) 1996-06-25 1996-06-25 Method of forming thin film transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960023636A KR100201781B1 (en) 1996-06-25 1996-06-25 Method of forming thin film transistor

Publications (2)

Publication Number Publication Date
KR980005879A true KR980005879A (en) 1998-03-30
KR100201781B1 KR100201781B1 (en) 1999-06-15

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KR100201781B1 (en) 1999-06-15

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