KR920003468A - Morse manufacturing method using two-layer polycrystalline silicon film - Google Patents

Morse manufacturing method using two-layer polycrystalline silicon film Download PDF

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Publication number
KR920003468A
KR920003468A KR1019900010432A KR900010432A KR920003468A KR 920003468 A KR920003468 A KR 920003468A KR 1019900010432 A KR1019900010432 A KR 1019900010432A KR 900010432 A KR900010432 A KR 900010432A KR 920003468 A KR920003468 A KR 920003468A
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KR
South Korea
Prior art keywords
polycrystalline silicon
morse
gate
silicon film
manufacturing
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KR1019900010432A
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Korean (ko)
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KR930002059B1 (en
Inventor
권호엽
Original Assignee
문정환
금성일렉트론 주식회사
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Priority to KR1019900010432A priority Critical patent/KR930002059B1/en
Publication of KR920003468A publication Critical patent/KR920003468A/en
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Publication of KR930002059B1 publication Critical patent/KR930002059B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

내용 없음.No content.

Description

2층의 다결정 실리콘막을 이용한 모스 제조방법Morse manufacturing method using two-layer polycrystalline silicon film

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 종래의 구성 단면도.1 is a cross-sectional view of a conventional configuration.

제2도는 본 발명의 공정 단면도.2 is a cross-sectional view of the process of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 기판 2 : 필드산화막1 substrate 2 field oxide film

3 : 질화막 4 : 다결정 실리콘막3: nitride film 4: polycrystalline silicon film

5,7 : 산화막 6 : 측벽 스페이서5,7 oxide film 6: sidewall spacer

Claims (1)

기판에 액티브 영역을 한정하고 필드산화를 행하는 단계와, 질화막/다결정 실리콘막/산화막을 차례로 증착하는 단계, 게이트 영역의 한정을 위해 상기 3층막을 식각하는 단계, 소오스/드레인 영역 형성을 위해 상기 질화막을 일정크기 만큼 더 식각하는 단계, 상기 일정크기 만큼 더 식각된 질화막의 부위에 이온주입을 행하여 소오스/드레인 영역을 형성한 다음 다결정 실리콘을 채우는 단계, 게이트와 소오스/드레인 사이를 절연시키기 위해 산화막의 측벽 스페이서를 형성하는 단계, 한정된 게이트 영역에 다결정 실리콘을 증착하여 게이트를 한정하는 단계가 순차적으로 이루어짐을 특징으로 하는 모스 트랜지스터의 제조방법.Defining an active region on the substrate and performing field oxidation, depositing a nitride film / polycrystalline silicon film / oxide film in sequence, etching the three-layer film to define a gate region, and forming the nitride film to form a source / drain region Etch more by a predetermined size, ion implantation into a portion of the nitride film etched by a predetermined size to form a source / drain region, and then fill polycrystalline silicon, and insulate between the gate and the source / drain Forming a sidewall spacer, and depositing polycrystalline silicon in a defined gate region to define a gate sequentially. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900010432A 1990-07-10 1990-07-10 M.o.s. manufacturing method using polysilicon KR930002059B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900010432A KR930002059B1 (en) 1990-07-10 1990-07-10 M.o.s. manufacturing method using polysilicon

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900010432A KR930002059B1 (en) 1990-07-10 1990-07-10 M.o.s. manufacturing method using polysilicon

Publications (2)

Publication Number Publication Date
KR920003468A true KR920003468A (en) 1992-02-29
KR930002059B1 KR930002059B1 (en) 1993-03-22

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900010432A KR930002059B1 (en) 1990-07-10 1990-07-10 M.o.s. manufacturing method using polysilicon

Country Status (1)

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KR (1) KR930002059B1 (en)

Also Published As

Publication number Publication date
KR930002059B1 (en) 1993-03-22

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