KR980005446A - 저누설전류특성을 갖는 실리콘기판에의 얕은 접합층 형성방법 - Google Patents

저누설전류특성을 갖는 실리콘기판에의 얕은 접합층 형성방법 Download PDF

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KR980005446A
KR980005446A KR1019960021804A KR19960021804A KR980005446A KR 980005446 A KR980005446 A KR 980005446A KR 1019960021804 A KR1019960021804 A KR 1019960021804A KR 19960021804 A KR19960021804 A KR 19960021804A KR 980005446 A KR980005446 A KR 980005446A
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South Korea
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ions
substrate
forming
silicon substrate
ion implantation
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KR1019960021804A
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KR100270073B1 (ko
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김광일
권영규
정욱진
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김종진
포항종합제철 주식회사
신창식
재단법인 산업과학기술연구소
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Priority to KR1019960021804A priority Critical patent/KR100270073B1/ko
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Weting (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 반도체소자의 제조공정에 관한 것이며, 그 목적을 불순물이온 주입전에 불활성 이온을 이중주입하여 먼저 점결합 크로스터층을 만들고 다음에 표면에 얕은 비정질층을 형성하므로써, 누설전류특성이 양호한 실리콘기판에의 얕은 접합층 형성방법을 제공함에 있다. 상기 목적달성을 위한 본 발명은 반도체소자의 제조방법에 있어서, 실리콘 기판에 SiO2산화막을 형성한 후 이온이 주입되는 부위를 에칭제거하는 단계; 상기 이온주입부위를 통해 불순물(dopant)이온을 주입하기전에, 그 불순물의 비정거리 이상까지 먼저 점결함 크러스터들을 기판내부에 과잉발생시키고 다시 기판의 표면부근에 얕은 비정질층을 형성하기 위하여 실리콘 이온 또는 게르마늄이온을 이중이온주입 하는 단계; 상기 이온주입 부위를 통하여 기판내에 불순물이온을 주입하는 단계; 및 질소분위기하에서 급속열처리하여 확산영역을 형성하는 단계;를 포함하여 구성되는 저누설전류특성을 갖는 실리콘기판에의 얕은 접합층 형성방법에 관한 것을 그 요지로 한다.

Description

저누설전류특성을 갖는 실리콘기판에의 얕은 접합층 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도는 본 발명(a)및 종래(b) 방법으로 선이온주입시 급속열처리에 따른 점결함의 분포를 보여주는 전자현미경사진.

Claims (3)

  1. 반도체소자의 제조방법에 있어서, 실리콘 기판에 SiO2산화막을 형성한 후 이온이 주입되는 부위를 에칭제거하는 단계; 상기 이온주입부위를 통해 불순물(dopant)이온을 주입하기전에, 그 불순물의 비정거리 이상까지 먼저 점결함 크러스터들을 기판내부에 과잉발생시키고 다시 기판의 표면부근에 얕은 비정질층을 형성하기 위하여 실리콘 이온 또는 게르마늄이온을 이중 이온주입 하는 단계; 상기 이온주입 부위를 통하여 기판내에 불순물이온을 주입하는 단계; 및 질소분위기하에서 급속열처리하여 확산영역을 형성하는 단계;를 포함하여 구성됨을 특징으로 하는 저누설전류특성을 갖는 실리콘기판에의 얕은 접합층 형성방법.
  2. 제1항에 있어서, 상기 기판은 n형 실리콘기판이고 상기 불순물은 붕소(B)임을 특징으로 하는 방법.
  3. 제1항 또는 제2항에 있어서, 상기 실리콘이온 또는 게르마늄이온의 주입은 먼저 1×1015/㎠이하의 도우즈량으로 주입하고 그 보다 낮은 에너지에서 1×1015/㎠의 도우즈량으로 다시 주입함을 특징으로 하는 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960021804A 1996-06-17 1996-06-17 저누설전류특성을 갖는 실리콘기판에의 얕은 접합층 형성방법 KR100270073B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960021804A KR100270073B1 (ko) 1996-06-17 1996-06-17 저누설전류특성을 갖는 실리콘기판에의 얕은 접합층 형성방법

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Application Number Priority Date Filing Date Title
KR1019960021804A KR100270073B1 (ko) 1996-06-17 1996-06-17 저누설전류특성을 갖는 실리콘기판에의 얕은 접합층 형성방법

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KR980005446A true KR980005446A (ko) 1998-03-30
KR100270073B1 KR100270073B1 (ko) 2000-10-16

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