KR970072400A - Method for manufacturing nonvolatile memory device - Google Patents

Method for manufacturing nonvolatile memory device Download PDF

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Publication number
KR970072400A
KR970072400A KR1019960010273A KR19960010273A KR970072400A KR 970072400 A KR970072400 A KR 970072400A KR 1019960010273 A KR1019960010273 A KR 1019960010273A KR 19960010273 A KR19960010273 A KR 19960010273A KR 970072400 A KR970072400 A KR 970072400A
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South Korea
Prior art keywords
forming
cell array
array portion
insulating film
bit line
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KR1019960010273A
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Korean (ko)
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KR100195210B1 (en
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강정의
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김광호
삼성전자 주식회사
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

비트라인의 분리특성을 강화시킨 불휘발성 메모리장치의 제조방법에 대해 기재되어 있다. 이는, 셀 배열부 및 주변회로부의 반도체기판의 비활성영역에 필드절연막을 형성하는 단계, 셀 배열부의 활성영역에 플로팅 게이트, 유전체막 및 컨트롤 게이트로 구성되는 게이트와, 소오스/드레인을 구비하는 셀 트랜지스터를 형성하는 단계, 주변회로부의 활성영역에 게이트, 소오스 및 드레인을 구비하는 트랜지스터를 형성하는 단계, 셀 배열부 및 주변회로부의 상기 결과물 상에 층간절연막을 형성하는 단계, 셀 배열부의 층간절연막을 부분적으로 식각하여, 비트라인과 반도체기판의 활성영역을 접속시키기 위한 콘택홀을 형성하는 단계, 셀 배열부 및 주변회로부의 결과물 상에 비트라인을 형성하기 위한 도전층을 형성하는 단계, 도전층을 패터닝하여 비트라인을 형성하는 단계 및 반도체기판에 채널스톱용 불순물이온을 주입하는 단계를 포함하는 것을 특징으로 한다. 따라서, 채널스톱 불순물층을 비트라인에 자기정합적으로 형성할 수 있으므로 공정을 단순화할 수 있으며, 열 공정을 덜 거치게 되므로 필드산화막 형성시 고온에 의한 불순물 확산을 감소시켜 소자분리 특성을 개선할 수 있다.A method of manufacturing a nonvolatile memory device in which isolation characteristics of bit lines are enhanced is described. The method includes the steps of forming a field insulating film in an inactive region of a semiconductor substrate of a cell array portion and a peripheral circuit portion, forming a field insulating film in a cell array portion and a peripheral portion of the cell transistor, Forming a transistor having a gate, a source, and a drain in an active region of the peripheral circuit portion; forming an interlayer insulating film on the result of the cell array portion and the peripheral circuit portion; Forming a contact hole for connecting the bit line and the active region of the semiconductor substrate, forming a conductive layer for forming a bit line on the result of the cell array portion and the peripheral circuit portion, Forming a bit line and implanting impurity ions for channel stop into the semiconductor substrate; And it characterized in that. Therefore, since the channel stopper impurity layer can be formed on the bit line in a self-aligning manner, the process can be simplified and the thermal process can be performed less, so that the device isolation characteristic can be improved by reducing impurity diffusion due to high temperature have.

Description

불휘발성 메모리장치의 제조방법Method for manufacturing nonvolatile memory device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제5A도 내지 제5E도는 본 발명의 일 실시예에 의한 불휘발성 메모리장치의 제조방법을 설명하기 위한 단면도들이다. 제6A도 내지 제6D도는 본 발명의 다른 실시예에 의한 불휘발성 메모리장치의 제조방법을 설명하기 위한 단면도들이다.5A to 5E are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device according to an embodiment of the present invention. FIGS. 6A to 6D are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device according to another embodiment of the present invention.

Claims (7)

셀 배열부 및 주변회로부위 반도체기판의 비활성영역에 필드절연막을 형성하는 단계; 상기 셀 배열부의 활성영역에 플로팅 게이트, 유전체막 및 컨트롤 게이트로 구성되는 게이트와, 소소/드레인을 구비하는 셀 트랜지스터를 형성하는 단계; 상기 주변회로부의 활성영역에 게이트, 소오스 및 드레인을 구비하는 트랜지스터를 형성하는 단계; 셀 배열부 및 주변회로부의 상기 결과물 상에 층간절연막을 형성하는 단계; 상기 셀 배열부의 층간절연막을 부분적으로 식각하여, 비트라인과 반도체기판의 활성영역을 접속시키기 위한 콘택홀을 형성하는 단계; 상기 셀 배열부 및 주변회로부의 결과물 상에 비트라인을 형성하기 위한 도전층을 형성하는 단계; 상기 도전층을 패터닝하여 비트라인을 형성하는 단계; 및 상기 반도체기판에 채널스톱용 불순물이온을 주입하는 단계를 포함하는 것을 특징으로 하는 불휘발성 메모리장치의 제조방법.Forming a field insulating film in an inactive region of the cell array portion and the peripheral circuit region semiconductor substrate; Forming a cell transistor having a gate composed of a floating gate, a dielectric film, and a control gate and a source / drain in an active region of the cell array portion; Forming a transistor having a gate, a source, and a drain in an active region of the peripheral circuit; Forming an interlayer insulating film on the resultant structure of the cell array portion and the peripheral circuit portion; Forming a contact hole for partially connecting the bit line to the active region of the semiconductor substrate by partially etching the interlayer insulating film of the cell array portion; Forming a conductive layer for forming a bit line on the result of the cell array portion and the peripheral circuit portion; Patterning the conductive layer to form bit lines; And implanting impurity ions for channel stop into the semiconductor substrate. ≪ RTI ID = 0.0 > 11. < / RTI > 제1항에 있어서, 상기 셀 배열부의 층간절연막을 식각하는 공정은, 상기 층간절연막을 소정 두께 습식식각한 후 건식식각하는 것을 특징으로 하는 불휘발성 메모리장치의 제조방법.The method of manufacturing a nonvolatile memory device according to claim 1, wherein the step of etching the interlayer insulating film in the cell array portion comprises dry etching the interlayer insulating film after wet etching the predetermined thickness. 제1항에 있어서, 상기 셀 배열부의 층간절연막을 식각하는 공정은, 건식식각에 의해 이루어지는 것을 특징으로 하는 불휘발성 메모리장치의 제조방법.The method for manufacturing a nonvolatile memory device according to claim 1, wherein the step of etching the interlayer insulating film of the cell array portion is performed by dry etching. 제1항에 있어서, 상기 채널스톱용 불순물이온을 주입하는 단계는, 상기 비트라인 도전층 패터닝시 사용된 마스크를 그대로 식각마스크로 사용하여 진행되는 것을 특징으로 하는 불휘발성 메모리장치의 제조방법.The method of claim 1, wherein implanting the channel stop impurity ions is performed by using a mask used for patterning the bit line conductive layer as it is as an etching mask. 제1항에 있어서, 상기 채널스톱 불순물이온을 주입하는 단계는, 상기 비트라인 도전층 패터닝시 사용된 감광막패턴을 제거하는 단계; 그 결과물 상에 통상의 사진공정에 의해 셀 배열부만을 개방하는 감광막패턴을 형성하는 단계; 및 상기 감광막패턴을 이온주입 마스크로 사용하여 불순물 이온을 주입하는 단계로 이루어지는 것을 특징으로 하는 불휘발성 메모리장치의 제조방법.2. The method of claim 1, wherein implanting the channel stop impurity ions further comprises: removing a photoresist pattern used in patterning the bit line conductive layer; Forming a photoresist pattern that opens only the cell array portion on the resultant by a normal photolithography process; And implanting impurity ions using the photoresist pattern as an ion implantation mask. 제1항에 있어서, 상기 비트라인을 형성하기 위한 도전층은 도우프된 폴리실리콘, 폴리실리콘과 실리사이드가 순차적으로 적층된 폴리사이드 및 금속 중의 어느 한 구조로 이루어진 것을 특징으로 하는 불휘발성 메모리장치의 제조방법.The nonvolatile memory device according to claim 1, wherein the conductive layer for forming the bit line is formed of a doped polysilicon, a polycide in which polysilicon and silicide are sequentially stacked, and a metal. Gt; 제1항에 있어서, 상기 채널스톱 불순물이온을 230KeV 정도의 주입 에너지로 주입하는 것을 특징으로하는 불휘발성 메모리장치의 제조방법.The method of manufacturing a nonvolatile memory device according to claim 1, wherein the channel stop impurity ions are implanted at an implantation energy of about 230 KeV. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960010273A 1996-04-04 1996-04-04 Method for forming nonvolatile memory device KR100195210B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100680455B1 (en) * 2005-06-30 2007-02-08 주식회사 하이닉스반도체 A NAND type flash memory device and Method of manufacturing and operating the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100680455B1 (en) * 2005-06-30 2007-02-08 주식회사 하이닉스반도체 A NAND type flash memory device and Method of manufacturing and operating the same
US7310267B2 (en) 2005-06-30 2007-12-18 Hynix Semiconductor Inc. NAND flash memory device and method of manufacturing and operating the same

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