KR100195210B1 - Method for forming nonvolatile memory device - Google Patents

Abstract

A method of manufacturing a nonvolatile memory device having enhanced bit line isolation characteristics is described.

The method includes forming a field insulating film in an inactive region of a semiconductor substrate of a cell array unit and a peripheral circuit unit, a cell including a floating gate, a dielectric layer and a gate as a gate, and a source / drain in the active region of the cell array unit. Forming a transistor, forming a transistor having a gate, a source, and a drain in an active region of the peripheral circuit portion, forming an interlayer insulating film on the resultant cell array portion and the peripheral circuit portion, and forming an interlayer insulating layer on the cell array portion. Partially etching to form a contact hole for connecting the bit line with the active region of the semiconductor substrate, forming a conductive layer for forming the bit line on the cell array and the peripheral circuit portion, and forming a conductive layer. Forming a bit line under patterning and implanting impurity ions for channel stop into the semiconductor substrate; And it characterized in that.

Therefore, since the channel stop impurity layer can be formed on the bit line in a self-aligned manner, the process can be simplified, and the heat treatment process can be simplified, and thus, the isolation characteristics of the device can be improved by reducing impurity diffusion due to high temperature when forming the field oxide film. have.

Description

Manufacturing method of nonvolatile memory device

1 is a layout diagram of a general NAND type nonvolatile memory cell.

2 is a layout diagram of a nonvolatile memory cell according to a conventional method proposed to improve device isolation characteristics.

3 to 4b are cross-sectional views illustrating a method of manufacturing a conventional nonvolatile memory device for improving device isolation characteristics, and FIGS. 4a and 4b show AA 'and B-B's layout diagrams of FIG. 'This is a cross-sectional view of each line.

5A through 5E are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with an embodiment of the present invention.

6A through 6D are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with another embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to a method of manufacturing a NAND type nonvolatile memory device having improved electrical device isolation characteristics of a bit line.

Recently, highly integrated nonvolatile memory, that is, flash memory, is expected to replace a magnetic disk because it has advantages such as small cell size and fast access time.

In general, a nonvolatile memory includes one transistor composed of a source electrode, a drain, and a gate electrode formed of a floating gate and a control gate. Here, the floating gate serves to store data, the control gate serves to control the floating gate, and a high-voltage signal is applied to the control gate and the pocket well to program and store the data. It has a feature that enables erasing.

In order to increase the density of the nonvolatile memory, the cell size must be made small, which is a problem of reducing the width and spacing of the word line on one side of the cell, and a problem of reducing the spacing between the bit lines on the other side. The distance between the bit lines is determined by the width of the active area formed in the same direction as the bit line and the separation distance between the active areas. In particular, since the bit lines and the adjacent bit lines must be separated from each other, It is difficult to reduce the separation distance.

In order to solve this problem, many methods have been proposed to reduce the cell size by improving the device isolation characteristics between the bit lines and reducing the separation distance between the active regions. An example thereof will be described with reference to the drawings.

1 is a layout diagram of a general NAND type nonvolatile memory cell.

Referring to FIG. 1, a region in which a memory cell is formed and an isolation region are determined by the active region 110, and a word line 120 and a select line are perpendicular to the active region. 130 and the like, and a word line is configured to have one floating gate (reference numeral F) for each cell, and the plurality of weed lines is formed. Each active region is electrically connected between the bit line 140 and the selection line (in this case, the string selection line) via a contact 150.

2 is a layout diagram of a conventional NAND type nonvolatile memory cell proposed to improve device isolation characteristics (US Pat. No. 5,172,198, inventor: Seiichi Aritome et al., December 15, 1992, title: MOS) Type Semiconductor Device). The portions except the hatched portions represent portions to be implanted with channel stop ions for improving device isolation characteristics.

3 to 4b are cross-sectional views illustrating a method of manufacturing a NAND type nonvolatile memory device according to a conventional method proposed to improve device isolation characteristics, and FIGS. 3 and 4a are A of FIG. Fig. 4B is a cross-sectional view taken along the line A-A ', and Fig. 4B is a cross-sectional view taken along the line B-B'.

A device isolation and cell formation method according to a conventional method will be described with reference to FIGS. 2 to 4b.

3 is a cross-sectional view showing an ion implantation step for channel stop.

In detail, a first step of forming a well having a predetermined depth by ion diffusion of N-type and P-type impurities into the P-type semiconductor substrate 10 and then by high temperature diffusion, a typical selective oxidation (Local Oxidation) In order to form a field oxide film having a device-to-device separation function by silicon (LOCOS), a second process and a predetermined photolithography process of laminating a pad oxide film 12 and a nitride film 14 to a predetermined thickness on the semiconductor substrate are performed. A third process of forming the nitride film pattern 14 by etching the nitride film in the non-active region, and using the nitride film pattern 14 as an ion implantation mask to enhance device isolation characteristics. A fourth step of forming the first ion implantation layer 16 by primary ion implantation of an impurity of, for example, boron (B) with energy of 100 KeV and a dose of 7 × 10 ¹² ions / cm 2 And mask for combing channel stop ion implantation of FIG. A fifth step of forming a photoresist pattern 18 exposing only a portion corresponding to a central portion of the device isolation region using the painted portion), and using the photoresist pattern 18 as an ion implantation mask, boron the semiconductor substrate. (B) Proceeds to the sixth step of forming the second ion implantation layer 20 by secondary ion implantation with energy of 100 KeV and a dose of 3x10 ¹³ ions / cm 2.

4A is a cross-sectional view showing the step of forming the field oxide film 22.

Specifically, the first step of removing the photoresist pattern (18 in FIG. 3) used as the secondary ion implantation mask, and the high temperature oxidation process using the nitride film pattern (14 in FIG. 3) as the oxidation inhibiting layer A second process of forming a field oxide film 22 for isolation between devices on a semiconductor substrate and a third process of removing the nitride film pattern (14 of FIG. 3) are performed.

Through the process of forming the field oxide film 22, impurities of the first and second ion implantation layers 16 and 20 formed in the previous step are activated to channel stops of P type and high concentration P type (P ⁺ ), respectively. Impurity layers 16a and 20a are formed.

As shown in FIG. 4A, the channel stop impurity layer may include a first impurity layer 16a that is primarily aligned with the field oxide film 22 and a photoresist pattern at the center of the field oxide film 22. It is comprised by the 2nd impurity layer 20 implanted by ion limited by 18 of FIG. Since the second impurity layer 20 has a higher concentration than the first impurity layer 16, the device isolation characteristics and the field threshold voltage (V _th ) can be improved.

However, in the conventional method described above, referring to FIG. 4B, which is a vertical cross-sectional view of the cut line BB 'of FIG. 2, that is, the region where the bit line contact is formed, an opening for channel stop ion implantation is formed on the field oxide film. As shown in FIG. 3, additional impurity implantation by the second impurity ion implantation process is impossible, resulting in only the first impurity layer 16 being formed. This is because the device isolation characteristic of the portion where the bit line contact is formed is determined only by the first impurity layer 16, and has a channel stop shape different from that of the cell array of FIG. 4a. There is a problem in that it is difficult to apply to a highly integrated nonvolatile memory cell of sub-micron level or higher.

When the dose of the first impurity is increased to improve the device isolation characteristic of the region, the impurity implanted to form the channel stop layer is diffused to the channel region of the memory cell transistor through several heat treatment processes until the final process. As a result, the effective channel width of the cell transistor is reduced, so that the cell driving current is reduced and the junction breakdown voltage is reduced.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a method of manufacturing a nonvolatile memory device capable of improving electrical isolation characteristics of a bit line without using a separate mask.

The manufacturing method of the nonvolatile memory device for achieving the object of the present invention,

Forming a field insulating film in an inactive region of the semiconductor substrate of the cell array unit and the peripheral circuit unit;

Forming a cell transistor including a floating gate, a dielectric film, and a control gate in an active region of the cell array, and a source / drain;

Forming a transistor having a gate, a source, and a drain in an active region of the peripheral circuit portion;

Forming an interlayer insulating film on the resultant cell arrangement and peripheral circuit portion;

Partially etching the interlayer insulating film of the cell array to form a contact hole for connecting the bit line and the active region of the semiconductor substrate;

Forming a conductive layer for forming a bit line on the resultant of the cell array unit and the peripheral circuit unit;

Patterning the conductive layer to form a bit line; And

And implanting impurity ions for channel stop into the semiconductor substrate.

The etching of the interlayer insulating film of the cell array unit may be performed by dry etching, or may be dry etching after wet etching the small interlayer insulating film.

The implanting of impurity ions for channel stop may be performed by using a mask used for patterning the bit line conductive layer as an etching mask or removing the photoresist pattern used for patterning the bit line conductive layer; Forming a photoresist pattern on the resultant, which opens only the cell array portion by a normal photographic process; And implanting impurity ions using the photoresist pattern as an ion implantation mask.

The conductive layer for forming the bit line may be formed of any one of doped polysilicon, polysilicon and metal in which polysilicon and silicide are sequentially stacked, and the channel stop impurity ions are injected at an injection energy of about 230 KeV. It is desirable to.

According to the present invention, by performing the impurity ion implantation process for the channel stop together with the bit line patterning process, the channel stop impurity layer can be self-aligned to the bit line, thereby simplifying the process. Since the process is less processed, it is possible to improve the device isolation characteristics by reducing impurity diffusion due to high temperature when forming the field oxide film.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail.

[First Embodiment]

5A through 5E are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with a first embodiment of the present invention.

5A is a cross-sectional view showing the step of forming the field oxide films 35 and 36.

Specifically, N-type impurities are implanted into a predetermined area of the peripheral circuit portion and the cell array portion of the semiconductor substrate 30 using conventional photolithography and ion implantation techniques, and then subjected to high temperature heat treatment to diffuse to a desired depth. Form wells. Subsequently, field oxide films 35 and 36 for electrical separation between devices are formed by a conventional device isolation process such as, for example, a selective oxidation method (LOCOS).

At this time, since the peripheral circuit portion has a wide pattern spacing and the cell array portion has a small pattern spacing, the field oxide film 35 of the cell array portion is more thin than the field oxide film 36 of the peripheral circuit portion due to the field oxide thinning effect. It is thinly formed.

The field oxide thinning effect is a phenomenon in which the thickness of the field oxide film is changed depending on the width of the pattern of the site where the field oxidation occurs. The smaller the width of the pattern is, the thinner the thickness is. For example, when the width of the pattern is 0.7 μm / 0.2 μm, when the field oxide film is grown by about 3,000 μs, the growth of the field oxide film is about 3,5000 μm / 1,100 μm. .

5B is a cross-sectional view illustrating a step of forming a cell transistor.

In detail, a thin thermal oxide film is deposited on the entire surface of the resultant in which the field oxide films 35 and 36 are formed to form a gate oxide film, polycrystalline silicon is deposited on the gate oxide film, and then a POCL ₃ is deposited. Doping lowers the resistance of the polysilicon, or deposits the polysilicon doped in-situ. After forming a floating gate by patterning the polysilicon layer using a conventional photolithography process, an oxide film, a nitride film, or an insulating film is formed to have a predetermined capacitance while insulating the floating gate and a control gate which becomes a word line of a cell. A dielectric film composed of a composite film of an oxide film and a nitride film is formed. Subsequently, polycrystalline silicon and tungsten silicide (WSix) are sequentially applied onto the dielectric film, and then the word line, the dielectric film, and the floating gate are sequentially etched by using a photolithography process, and then source / generated by a conventional ion implantation process. The drain 40 is formed.

In the floating gate forming process, with the floating gate layer on the field oxide layer 35 completely removed, an etching process is performed on the tungsten silicide layer / polycrystalline silicon layer / dielectric film / floating gate layer continuously. At this time, in order to completely remove the dielectric film on the floating gate, since the dielectric film is etched by the thickness of the floating gate, the exposed field oxide film is etched by a predetermined thickness. As a result, the field oxide film 35 of the cell array portion becomes thinner by 2,000 Å or more than the field oxide film 36 of the peripheral circuit portion.

Since FIG. 5B is a cross-sectional view of a bit line contact portion where a gate is not formed, the floating gate, the dielectric film, and the control gate do not appear in the figure.

5C is a cross-sectional view illustrating the steps of forming the interlayer insulating films 50 and 51.

Specifically, in the resultant product in which the cell transistor is formed, after forming the MOS transistor in the peripheral circuit region using a conventional transistor forming method, the cell array and the peripheral portion for electrical insulation with the bit line conductive layer to be formed thereon. On the resulting product of the circuit portion, for example, a high temperature oxide film (HTO) is deposited in a thickness of about 1,000 GPa and a boron-phosphorus silicon film (BPSG) in a thickness of about 3,500 kPa in order to form the interlayer insulating films 50 and 51.

5D is a cross-sectional view illustrating a step of forming the bit line contact hole 60.

Specifically, after performing the usual photolithography process using a mask pattern for forming a bit line contact to form the photoresist pattern 55, the interlayer insulating film 50 is removed by wet etching at least 1,000 Å, and then anisotropic dry type By completely removing the interlayer insulating film remaining in the portion where the contact hole is to be formed by etching, the contact hole 60 for connecting the bit line and the active region of the semiconductor substrate is formed.

At this time, the peripheral circuit area is protected by the photosensitive film 55, and etching is performed only in the cell array portion. In addition, when the wet etching is performed using the photoresist pattern as a mask in the interlayer insulation layer etching process of the cell array unit, an etchant penetrates under the rka photoresist pattern, thereby partially etching the interlayer insulation layer under the photoresist pattern. Therefore, in the step of forming the bit line contact, the interlayer insulating film 50 of the cell array portion and the interlayer insulating film 51 of the peripheral circuit region may have a thickness of 1,000 Å or more.

5E is a cross-sectional view illustrating the step of forming the bit line 65.

In detail, a conductive material for forming a bit line, for example, polysilicon or polysilicon and silicide is sequentially laminated on the resultant in which the contact hole is formed, and the conductive layer having a polyside structure is deposited for thousands of microseconds or more, and then ion implantation is performed. By doping the conductive layer to form a bit line conductive layer.

Subsequently, the bit line conductive layer is patterned by performing a photolithography process using a mask pattern for forming a bit line, thereby forming a bit line 65 overlapping the active region of the cell array unit.

Subsequently, impurity ions, such as boron ions, of opposite conductivity type to the substrate are implanted into the semiconductor substrate using the photoresist pattern 70 for patterning the bit line to form a channel stop ion implantation layer. . At this time, the energy for injecting the impurity ions must be properly adjusted so that only the cell array portion is injected and the peripheral circuit portion is not injected. According to the exemplary embodiment of the present invention, since the interlayer insulating film and the field oxide film of the cell array portion have a thickness of 2,000 Å or more than the field oxide film and the interlayer insulating film of the peripheral circuit part when the field oxide film is formed and the bit line contact hole is formed, The ion implantation energy is preferably 230 KeV.

In the ion implantation process, the active region is blocked by the photoresist film to prevent the implantation of ions. However, since the photoresist film is opened at the field oxide film portion, impurity ions penetrate the interlayer insulating film 50 and the field oxide film 35 to allow the field oxide film 35 to be implanted. It is injected into the lower semiconductor substrate 30 to serve as a channel stop for preventing punchthrough between the active regions of the bit line contact portions and punchthrough between the active regions of the portions other than the bit line contacts.

Although not shown, after the ion implantation process, an insulating layer for insulating the upper conductive layer is formed, and channel stop ions implanted during the leveling process through reflow are activated to form a channel stop region.

According to the method of fabricating the nonvolatile memory device according to the first embodiment of the present invention, the impurity ion implantation process for the channel stop is performed together with the bit line patterning process, so that the conventional channel stop ion implantation mask is separately used. Alternatively, the process can be simplified by using the bit line patterning mask as it is, and device isolation characteristics can be improved by reducing impurity diffusion due to high temperature when forming the field insulating film.

Second Embodiment

6A through 6D are cross-sectional views illustrating a method of manufacturing a NAND type nonvolatile memory device in accordance with a second embodiment of the present invention, wherein like reference numerals in FIGS. 5A through 5E denote the same parts.

FIG. 6A is a cross-sectional view illustrating a step of forming a field oxide film, a cell transistor, and an interlayer insulating film. Since the same method as that of the first embodiment of the present invention is performed, description thereof will be omitted. As described above in the first embodiment of the present invention, the field oxide film 35 of the cell array portion is thinner than the field oxide film 36 of the peripheral circuit portion.

6B is a cross-sectional view illustrating a step of forming a contact hole 60 for forming a bit line contact.

Specifically, after performing a photo process using a mask pattern for forming a bit line contact to form a photoresist pattern 55 for exposing the interlayer insulating film 35 on the bit line contact to the surface in the cell array portion, By using the photoresist pattern 55 as an etching mask, the interlayer insulating layer 35 of the exposed portion is anisotropically etched to form a contact hole 60 for connecting the bit line and the active region of the semiconductor substrate.

In comparison with the first embodiment of the present invention, the wet etching process for the interlayer insulating film is omitted.

6C is a cross-sectional view illustrating a step of forming the bit line 65.

Specifically, a conductive material for forming a bit line, for example, a polysilicon or a polyside structure, is deposited on the resultant in which the contact hole is formed, and then, by doping the conductive layer by ion implantation. A bit line conductive layer is formed. Subsequently, the bit line conductive layer is patterned by performing a photolithography process using a mispattern for forming a bit line, thereby forming a bit line 65 overlapping the active region of the cell array unit. Reference numeral 55, which is not described, denotes a photoresist pattern for patterning the bit line conductive layer.

6D is a cross-sectional view showing a step of injecting impurities for channel stop.

Specifically, after removing the photoresist pattern (55 in FIG. 6C) for patterning the bit line, the photolithography process is performed using a mask that opens only the cell array portion to mask the peripheral circuit portion, and then ion implantation for channel stop is performed. do. At this time, the active region is blocked by the impurity ions by the photosensitive film 70 and cannot be injected, and the impurity ions pass through the intermediate insulating film 50 and the field oxide film 35 to the semiconductor substrate 30 at the portion where the field oxide film is formed. It is injected to act as a channel stop layer to prevent punchthrough between the active regions of the bitline contact sites and punchthrough of the active regions formed parallel to portions other than the bitline contacts.

Although not shown, after the ion implantation process, an insulating layer for insulating the upper conductive layer is formed, and channel stop ions implanted during the leveling process through reflow are activated to form a channel stop region.

As described above, according to the manufacturing method of the nonvolatile memory device according to the present invention, the impurity ion implantation process for the channel stop is performed together with the bit line patterning process, so that the channel stop impurity layer is self-aligned to the bit line. Since it is possible to simplify the fixing, and less thermal process than the conventional process, it is possible to improve the device isolation characteristics by reducing the diffusion of impurities by high temperature when forming the field oxide film.

The present invention is not limited to the above embodiments, and many modifications are possible by those skilled in the art within the technical idea to which the present invention pertains.

Claims (7)

Forming a field insulating film in an inactive region of the semiconductor substrate of the cell array unit and the peripheral circuit unit; Forming a cell transistor including a floating gate, a dielectric film, and a control gate in an active region of the cell array, and a source / drain; Forming a transistor having a gate, a source, and a drain in an active region of the peripheral circuit portion; Forming an interlayer insulating film on the resultant cell arrangement and peripheral circuit portion; Partially etching the interlayer dielectric layer of the cell array to form a contact hole for connecting the bit line and the active region of the semiconductor substrate; Forming a conductive layer for forming a bit line on the resultant of the cell array unit and the peripheral circuit unit; Patterning the conductive layer to form a bit line; And implanting impurity ions for channel stop into the semiconductor substrate. The method of claim 1, wherein the etching of the interlayer dielectric layer of the cell array unit is performed by wet etching the interlayer dielectric layer after a predetermined thickness. The method of claim 1, wherein the etching of the interlayer dielectric layer of the cell array unit is performed by dry etching. The method of claim 1, wherein the implanting impurity ions for the channel stop is performed by using a mask used for patterning the bit line conductive layer as an etching mask. The method of claim 1, wherein the implanting of the channel stop impurity ions comprises: removing the photoresist pattern used during patterning of the bit line conductive layer; Forming a photoresist pattern on the resultant, which opens only the cell array portion by a normal photographic process; And implanting impurity ions using the photosensitive film pattern as an ion implantation mask. The nonvolatile memory device of claim 1, wherein the conductive layer for forming the bit line comprises one of a doped polysilicon, a polyside in which polysilicon and silicide are sequentially stacked, and a metal. Manufacturing method. The method of claim 1, wherein the channel stop impurity ions are implanted at an injection energy of about 230 KeV.