KR940009645B1 - Manufacturing method of non-volatile memory device - Google Patents

Abstract

A method includes the steps of forming a first conductive layer on a semiconductor substrate on which a field oxide layer, a gate oxide layer and a tunnel oxide layer are formed, sequentially forming an interlevel insulating layer, a second conductive layer and a first insulating layer on the first conductive layer, selectively etching the first insulating layer, forming a second insulating layer on the resultant, selectively exposing the second insulating layer, removing the second insulating layer, removing the exposed second conductive layer, the interlevel insulating layer and the first conductive layer, selectively etching the first insulating layer, second conductive layer, interlevel insulating layer and first conductive layer, forming a diffusion region on a predetermined portion of the substrate, forming a planarizing layer on the overall surface of the substrate, forming a contact hole through photolithography, and forming a metal layer on a predetermined portion.

Description

Manufacturing method of nonvolatile memory device

1A to 1D are sectional views showing the manufacturing process of the NAND type EEPROM cell array by the conventional method.

2 is a plan view showing a unit string of a conventional NAND type EEPROM.

3 is a plan view and an equivalent circuit diagram of a unit string of a NAND type EEPROM according to the present invention.

4A to 4H are process flowcharts showing a method for manufacturing a NAND type EEPROM cell array according to the present invention.

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a NAND type EEPROM.

Recent computer developments require the development of more integrated EEPROMs (Eliectrically erasable prog-ramable read only memory), and researches on NAND-type memory cells that can reduce the cell area without manufacturing difficulties have been continuously conducted. Coming.

A method of manufacturing a conventional NAND-type EEPROM introduced in "IEDM 1990, PP. 103-106" will now be described with reference to FIG. 1A.

The gate oxide film 3, the first polysilicon layer 4, the ONO film 5, and the second polysilicon layer 6 are sequentially formed on the n-type semiconductor substrate 1 on which the p-type well 2 is formed. After forming, the SiN film 7 is deposited on the second polysilicon layer 6 and patterned into a word line pattern by a photolithography process. At this time, the adjacent word lines are patterned one by one. That is, when the last word lines are arranged in a line, the SiN film 7 is patterned such that only patterns of odd word lines or even word lines are patterned (FIG. 1A).

Next, a photoresist pattern 8 having the same size as the pattern size of the patterned SiN film 7 is formed through the photolithography process again between the patterned SiN film 7 (FIG. 1B). This process is to complete the patterning before etching so that the word line under the SiN pattern and the word line under the photoresist pattern can be formed adjacent to each other.

Next, the second polycrystalline silicon layer 6, the ONO film 5 and the first polysilicon layer 4 are sequentially etched through a dry etching process to complete the word line (FIG. 1C).

Then, the remaining photoresist pattern is removed (FIG. 1a).

When the word line is formed by the above process, misalignment may occur in the process of forming the photoresist pattern between the SiN patterns. Therefore, margin for misalignment and minimum etching area for etching process should be secured. Therefore, the spacing between word lines can not be adjusted to be less than that. There is a problem that can not be formed at regular intervals because it varies depending on the misalignment or photolithography process conditions, that is, the exposure amount or the degree of development.

Accordingly, an object of the present invention is to provide a method of manufacturing a NAND type EEPROM cell array which can be reduced while maintaining a constant spacing between word lines in a NAND type EEPROM in which word lines run in parallel.

In order to achieve the above object, the present invention provides a method of manufacturing a NAND type EEPROM cell array in which a word line and a bit line are orthogonal and memory cells are connected in series between a string select line and a ground select line to form one memory string. A method of forming a semiconductor device, comprising: forming a first conductive layer on a semiconductor substrate of a first conductivity type in which a field oxide film, a gate oxide film, and a tunnel oxide film for device isolation are formed in predetermined regions, an interlayer insulating film on the first conductive layer, A step of sequentially stacking the second conductive layer and the first insulating film, and after etching the first insulating film of the portion corresponding to the even (or odd) word line in the continuous word line of the cell array by a photolithography process Forming a second insulating film on the entire surface, applying a photoresist on the entire surface of the resultant, and performing an etch back process to partially form the second insulating film. Exposing the second insulating layer, and then sequentially removing the second conductive layer, the interlayer insulating layer, and the first conductive layer to be exposed, and the string selection line and the word line adjacent to the ground selection line. The portion is limited to the photoresist, and then the first insulating film, the second conductive layer, the interlayer insulating film, and the first conductive layer of the other portions are sequentially etched, and a second conductive diffusion region is formed between the word lines. And a step of forming a planarization layer on the entire surface of the resultant, forming a contact region by a photolithography process, and then forming a metal layer on a predetermined region.

Hereinafter, the present invention will be described in more detail with reference to the drawings.

FIG. 2 is a plan view of a unit string composed of 8 bits of a conventional NAND type EEPROM, and FIG. 3 is a unit string plan view composed of 8 bits according to the present invention using the same design rule as that of FIG. An equivalent circuit diagram thereof is shown. In the cell structure of the EEPROM according to the present invention, as shown in FIG. 3, a bit line contact is connected to a drain of a string select transistor for selecting a unit string through an N ⁺ active region. The source of the string select transistor is connected in series to the drain of the storage cell through N ⁺ active region, and 8-bit cells are connected in sequence, and the ground line (GSL) of the unit string is connected. A drain of a ground select transistor for selecting is connected to a source of a cell located at the bottom of the bit line contact among the storage cells through an N ⁺ active region. In the above structure, the string select transistor, memory cell, and ground select transistor are connected to string select transistors, memory cells, and ground select transistors of adjacent unit strings by a conductive material such as polysilicon in a direction perpendicular to the bit line. (String select line; SSL), word lines (W / L1, ..., W / L8), and ground select line (GSL). Each line is electrically separated at regular intervals. Will be separated. Therefore, minimizing the distance between the string selection lines, the word lines, and the ground selection line running in parallel below the limit of the photo etching process can greatly reduce the area of the cell array (see FIGS. 2 and 3).

Since the operation of the NAND type EEPROM according to the present invention is the same as the conventional one, a description thereof will be omitted.

Next, the manufacturing method of the NAND type EEPROM cell array by this invention is demonstrated.

4A to 4H are sectional views showing the manufacturing method of the present invention according to the process sequence, taken along the line A-A 'in the plan view of FIG.

First, referring to FIG. 4A, a field oxide film 2 for device isolation on a first conductive type, for example, p-type semiconductor substrate 1 is formed by a conventional LOCOS process, followed by dry oxidation at 975 ° C. for 75 minutes. The gate oxide film 2 is grown to 350 mV, and boron is implanted under the condition of 8 x 10 ¹¹ ions / cm ² and 50 keV to adjust the threshold voltage. Subsequently, the memory cell region is defined by a photolithography process, and the gate oxide film 2 of the memory cell region is removed by wet etching, and As is adjusted to 2.5 × 10 ¹² ions / cm ² _{, in} order to adjust the threshold voltage of the cell _. Ion implantation under the condition of 30k. Here, reference numeral 4 denotes a photoresist.

Next, referring to FIG. 4B, the photoresist is removed, and then the tunnel oxide film 5 is grown at 100 DEG C. at 900 DEG C. Then, the first polysilicon layer 6 is deposited at 2000 DEG C. by LPCVD (Low pressure chemical vapor deposition) method. Then, the dopants such as PoCl ₃ are doped to lower the resistance of the polysilicon 6 to about 20Ω / □. Subsequently, referring to FIG. 4C, a process of forming an interlayer insulating film, such as an ONO (Oxide / Nitride / Oxide) film 7, on the first polycrystalline silicon layer 6 is performed. First, a bottom oxide film 900 is formed. The SiN film was grown on the first polycrystalline silicon layer 6 at 160 DEG C and then deposited by a 200 Å SiN film by LPCVD, followed by oxidation of the SiN film at 1000 DEG C for 10 minutes in a wet oxygen (Wet O ₂ ) atmosphere. The OND film 7 is completed by forming a top oxide film. Subsequently, a second polycrystalline silicon layer 8 is deposited on the ONO film 7 by 3000 Å and doped with impurities such as PoCl ₃ to lower the resistance to about 20? / ?, and then the WSi ₂ film 9 is placed on the second polysilicon layer ( 8) After the polyside is formed by vapor deposition on the film, the first insulating film, for example, the SiN film 10 is grown to 7000 Å. At this time, the thickness of the deposited SiN film 10 on the active region is adjusted to be thicker than the stack height of the first and second polycrystalline silicon on the field region.

Referring next to FIG. 4D, as a step of patterning a cell array region, only the even (or odd) word lines are patterned among successive word lines of the cell array, and thus the SiN film 10 of the corresponding portion is patterned. A 500 nm film of a second insulating film, such as a SiO ₂ film 11, is deposited on the remaining SiN film 10 after etching by the photolithography process and the exposed WSi ₂ film 9 by LPCVD. Then, the photoresist 12 is applied to the entire surface of the resultant and subjected to an etch back process to expose the SiO ₂ film 11. At this time, the SiO ₂ film on the SiN film presented for patterning the even word line is not exposed due to the step difference.

4E, the SiO ₂ film is removed by wet etching, and then the WSi ₂ film 9 and the second polysilicon layer 8 are formed using the photoresist 12 and the SiN film 10 as masks. The ONO film 7 and the first polysilicon layer 6 are sequentially removed by dry etching.

Referring next to FIG. 4F, the string select line, the portion of the word line adjacent to the ground select line, is limited to the photoresist 13, followed by the SiN film 10, the WSi film 9, and the second polycrystalline silicon. The cell array pattern is completed by etching the layer 8, the ONO film 7 and the first polycrystalline silicon layer 6 in sequence.

Next, referring to FIG. 4g, after the photoresist is removed, As is ion implanted under the condition of 6 × 10 ¹⁵ ions / cm ² 75 _, keV to form an N ⁺ active region between each word line. In order to activate the implanted ions, heat treatment is performed for 30 minutes in a dry oxygen (Dry O ₂ ) atmosphere at 950 ° C. At this time, an As concentration of about ^{1 × 10 14 ions / cm 2} , N - to form a region and N ⁺ region and the N ^- may form a region by ion implantation at the same time.

Subsequently, referring to FIG. 4h, a flattening layer, i.e., high temperature oxide (HTO) and borophosphsilicated glass (BPSG) 14, was deposited to a thickness of 1700 kPa and 7000 kPa, respectively, and reflowed in an N ₂ atmosphere at 925 ° C. After reflowing and planarization, the contact region is formed by a photolithography process, and then the metal layer 15 is formed in a predetermined region to complete the NAND type EEPROM according to the present invention. Here, reference numeral 16 denotes N ⁺ active region.

As described above, according to the present invention, the spacing between word lines in the NAND type EEPROM cell array can be reduced below the limit of the photolithography process, thereby greatly contributing to high integration of the semiconductor memory device.

Claims (13)

A method of manufacturing a NAND type EEPROM cell array in which a word line and a bit line are orthogonal and memory cells are connected in series between a string select line and a ground select line to form a single memory string, the field oxide film, the gate oxide film, Forming a first conductive layer on a first conductive semiconductor substrate each having a tunnel oxide film formed in a predetermined region, and sequentially laminating an interlayer insulating film, a second conductive layer, and a first insulating film on the first conductive layer; And etching the first insulating film of a portion corresponding to an even (or odd) word line among consecutive word lines of the cell array by a photolithography process to form a second insulating film on the entire surface of the resultant. Applying a toresist and performing an etch back process to partially expose the second insulating film; and removing the second insulating film. Removing the second conductive layer, the interlayer insulating film, and the first conductive layer exposed in sequence, and limiting the portion of the string selection line and the word line adjacent to the ground selection line with photoresist and then other portions. Etching the first insulating film, the second conductive layer, the interlayer insulating film, and the first conductive layer in order, forming a second conductive diffusion region between the word lines, and forming a planarization layer on the entire surface of the resultant. And forming a contact region by a photolithography process and then forming a metal layer in a predetermined region. The method of claim 1, wherein the first conductive layer is polycrystalline silicon formed by LPCVD. The method of manufacturing a nonvolatile memory device according to claim 1, wherein the interlayer insulating film is an ONO film. The method of claim 1, wherein the second conductive layer is formed of polyside. The method of claim 1, wherein the first insulating film is a SiN film. 6. The method of claim 5, wherein the SiN film is formed thicker than the thicknesses of the first and second conductive layers on the field region. The method of claim 1, wherein the second insulating film is a SiO ₂ film. The method of claim 1, wherein the removing of the second insulating layer is performed by wet etching. The method of manufacturing a nonvolatile memory device according to claim 1, wherein the step of removing the second conductive layer, the interlayer insulating film, and the first conductive layer performed after removing the second insulating film is performed by dry etching. The method of claim 1, wherein the diffusion region of the second conductivity type is formed as an N ⁺ region by implanting n-type impurities at a high concentration. The nonvolatile memory device of claim 1, wherein the diffusion region of the second conductivity type is formed of an N ⁻ region by implanting n-type impurities at a low concentration, or simultaneously formed of an N ⁺ region and an N ⁺ region. Manufacturing method. The method of claim 1, wherein the first insulating film and the second insulating film have different etching speeds. The method of claim 1, wherein the spacing between the word lines is controlled by a thickness of the second insulating layer.