KR19980075019A - Method of manufacturing nonvolatile semiconductor memory device - Google Patents
Method of manufacturing nonvolatile semiconductor memory device Download PDFInfo
- Publication number
- KR19980075019A KR19980075019A KR1019970011070A KR19970011070A KR19980075019A KR 19980075019 A KR19980075019 A KR 19980075019A KR 1019970011070 A KR1019970011070 A KR 1019970011070A KR 19970011070 A KR19970011070 A KR 19970011070A KR 19980075019 A KR19980075019 A KR 19980075019A
- Authority
- KR
- South Korea
- Prior art keywords
- conductor
- interlayer insulating
- etching
- insulating film
- oxide film
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 238000000034 method Methods 0.000 claims abstract description 52
- 239000004020 conductor Substances 0.000 claims abstract description 26
- 238000005530 etching Methods 0.000 claims abstract description 21
- 239000011229 interlayer Substances 0.000 claims abstract description 14
- 238000000151 deposition Methods 0.000 claims abstract description 13
- 230000015654 memory Effects 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 10
- 239000010703 silicon Substances 0.000 claims abstract description 10
- 238000002955 isolation Methods 0.000 claims abstract description 8
- 238000005468 ion implantation Methods 0.000 claims abstract description 6
- 238000002347 injection Methods 0.000 claims abstract description 3
- 239000007924 injection Substances 0.000 claims abstract description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 26
- 229920005591 polysilicon Polymers 0.000 claims description 26
- 150000004767 nitrides Chemical class 0.000 claims description 4
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 4
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 4
- 150000002500 ions Chemical class 0.000 claims description 3
- 239000010410 layer Substances 0.000 abstract description 6
- 238000000206 photolithography Methods 0.000 abstract description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 238000005086 pumping Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- AHKZTVQIVOEVFO-UHFFFAOYSA-N oxide(2-) Chemical compound [O-2] AHKZTVQIVOEVFO-UHFFFAOYSA-N 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32051—Deposition of metallic or metal-silicide layers
- H01L21/32053—Deposition of metallic or metal-silicide layers of metal-silicide layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76865—Selective removal of parts of the layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
Abstract
본 발명은 불휘발성 반도체 메모리 장치의 제조방법에 관한 것이다. 본 발명의 요지는 활성 영역과 소자분리 영역이 일정 간격으로 배열되며, 플로팅 게이트에 전자주입 또는 전자방출로 데이터를 저장하는 메모리 쎌과, 이와 연결되어 이를 선택하는 선택 트랜지스터를 가지는 불휘발성 반도체 메모리 장치의 제조방법에 있어서, 실리콘 기판위에 소자분리영역과 터널 산화막을 형성하는 과정과, 제1도전체를 침적하고 제1사진 공정을 진행한 후 제1도전체를 식각하는 과정과, 상기 제1도전체 상부에 제1층간절연막을 형성하고 제2도전체를 침적하는 과정과, 제2사진 공정 진행 후 상기 제2도전체, 제1층간절연막 및 제1도전체를 연속적으로 식각하는 과정과, 제3사진 공정 진행 후 제3도전체가 식각될 영역에 한정하여 이온주입하는 과정과, 전면에 제2층간절연막을 형성하는 과정과, 상기 제3도전체를 침적하는 과정과, 제4사진 공정 진행 후 상기 제3도전체를 식각하는 과정을 포함함을 특징으로 한다.The present invention relates to a method of manufacturing a nonvolatile semiconductor memory device. SUMMARY OF THE INVENTION The present invention provides a nonvolatile semiconductor memory device having an active region and a device isolation region arranged at regular intervals, having a memory 하는 storing data by electron injection or electron emission in a floating gate, and a selection transistor connected thereto to select the data. A method of fabricating a semiconductor device, the method comprising: forming a device isolation region and a tunnel oxide layer on a silicon substrate, depositing a first conductor, performing a first photolithography process, and then etching the first conductor; Forming a first interlayer insulating film on the upper body and depositing a second conductor; continuously etching the second conductor, the first interlayer insulating film, and the first conductor after the second photolithography process; After the photo process, the ion implantation is limited to the region where the third conductor is to be etched, the second interlayer insulating film is formed on the entire surface, the process of depositing the third conductor, and the fourth process. And etching the third conductor after the photographing process.
Description
본 발명은 불휘발성 반도체 메모리 장치에 관한 것으로, 특히 데이터를 저장하는 여러개의 메모리 쎌과 메모리 쎌을 선택하는 선택 트랜지스터가 낸드형태로 연결된 불휘발성 플래쉬 이이피롬(Flash EEPROM) 장치의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, and more particularly, to a method of manufacturing a nonvolatile flash EEPROM device in which a plurality of memory cells for storing data and a selection transistor for selecting the memory cells are connected in a NAND form. .
일반적으로, 이이피롬은 단결정 실리콘 기판위에 터널 산화막(Tunnel Oxide)으로 절연된 제1폴리실리콘(polysilicon)과 제1폴리실리콘 상부에 층간절연막으로 절연된 제2폴리실리콘이 적층된 구조의 다수개의 메모리 쎌로 구성되어 있다. 데이터의 저장 및 소거는 실리콘 기판과 제2폴리실리콘 사이에 적절한 전압을 인가함으로써 제1폴리실리콘에 전자를 주입하거나 방출하는 방법으로 이루어진다. 또한 이러한 제1폴리실리콘을 플로팅 게이트(Floating Gate)라 하며 제2폴리실리콘을 콘트롤 게이트(Control Gate)라 부른다. 데이터의 저장 및 소거시에는 실리콘 기판과 제1폴리실리콘사이에 일정전압 이상의 전위차가 유지되어야 하므로 실제 전압이 인가되는 제2폴리실리콘에 고전압이 인가되어야 한다. 고전압을 공급하기 위해서는 주변회로에 차아지 펌핑(charge pumping) 회로가 필요하며 이로 인하여 칩 사이즈(chip size)가 증가하고 전력소모가 증가하는 단점이 있다. 따라서 제2폴리실리콘에 인가되는 전압에 의해 제1폴리실리콘에 인가되는 전압의 비 즉, 커플링 비(coupling ratio)를 높여 터널링(tunneling)에 필요한 고전압을 낮추는 것이 중요하다. 커플링 비를 높이기 위해 제안된 구조가 승압 플레이트(pumping plate)를 이용한 구조로 1996년 VLSI의 238쪽 ∼ 239쪽에 개시되어 있으며 이에 따른 제조방법은 다음과 같다. 종래의 쎌 구조와 동일하게 쎌 어레이(Cell Array)내에 메모리 쎌 게이트(Memory Cell Gate)를 형성한다. 먼저 소자 분리막과 터널 산화막을 형성한다. 제1폴리실리콘을 침적한 후 사진공정과 식각공정을 이용하여 제1폴리실리콘 패턴(pattern)을 형성한다. 연속으로 층간절연막을 형성한 후 제2폴리실리콘을 침적한다. 센스앰프 기법으로 제2폴리실리콘, 층간절연막, 제1폴리실리콘을 연속으로 식각한다. 이로써 종래의 쎌 구조와 동일한 메모리 쎌 게이트를 형성하게 된다. 여기에 추가로 이미 형성된 메모리 쎌 상부 및 소오스(Source)/드레인(Drain) 영역에 화학기상증착법(Chemical Vapor Deposition)등을 통하여 산화막을 형성한 후 플레이트 폴리사이드(plate polycide)를 증착한다.In general, EPyrom has a plurality of memories having a structure in which a first polysilicon insulated with a tunnel oxide film on a single crystal silicon substrate and a second polysilicon insulated with an interlayer insulating film over the first polysilicon are stacked. It is composed of 쎌. The storage and erasure of data consists of a method of injecting or emitting electrons into the first polysilicon by applying an appropriate voltage between the silicon substrate and the second polysilicon. In addition, the first polysilicon is called a floating gate and the second polysilicon is called a control gate. When storing and erasing data, a potential difference of a predetermined voltage or more must be maintained between the silicon substrate and the first polysilicon, and a high voltage should be applied to the second polysilicon to which the actual voltage is applied. In order to supply a high voltage, a charge pumping circuit is required in a peripheral circuit, which results in an increase in chip size and power consumption. Therefore, it is important to lower the high voltage required for tunneling by increasing the ratio of the voltage applied to the first polysilicon, that is, the coupling ratio, by the voltage applied to the second polysilicon. The proposed structure to increase the coupling ratio is a structure using a pumping plate is disclosed on page 238 ~ 239 of VLSI in 1996, and the manufacturing method according to this is as follows. A memory cell gate is formed in a cell array in the same way as a conventional cell structure. First, a device isolation film and a tunnel oxide film are formed. After depositing the first polysilicon, a first polysilicon pattern is formed by using a photo process and an etching process. After forming the interlayer insulating film in succession, the second polysilicon is deposited. The second polysilicon, the interlayer insulating film, and the first polysilicon are sequentially etched by the sense amplifier technique. As a result, the memory pin gate of the conventional pin structure is formed. In addition, an oxide film is formed on the upper portion of the memory cell and the source / drain region, which are already formed, and then, a plate polycide is deposited through chemical vapor deposition.
사진공정과 식각공정을 통하여 메모리 쎌 어레이(Memory Cell Array)를 제외한 나머지 부분의 플레이트 폴리사이드를 제거해준다. 상기 방법에 의하여 형성된 승압 플레이트에 전압을 인가함으로써 커플링 비를 높이게 된다. 이때 이전 공정에서 형성된 트랜지스터의 단차에 의해서 쎌 측면에는 식각공정 중 제거해주어야 할 플레이트 폴리사이드가 많아진다. 많은 플레이트 폴리사이드를 제거하기 위해서 식각 공정을 진행하다 보면 상대적으로 비트라인 콘택 주위 및 공통 소오스 라인 같이 단차가 없어 플레이트 폴리사이드가 얇게 형성된 부분에서는 플레이트 폴리사이드와 하부의 산화막이 식각되어 실리콘 기판이 노출, 식각되는 문제점이 유발된다. 그러므로 플레이트 폴리사이드 하부의 산화막 두께를 증가시켜야 한다. 그러나 산화막의 두께가 증가하게 되면 상대적으로 산화막의 캐패시턴스값이 작아져서 승압 플레이트의 역할이 감소하게 되므로 두께를 올리는 데는 한계가 있다. 이러한 식각상의 문제는 승압 플레이트 쎌을 제조하는데 공정상의 어려움으로 남게 된다.Photolithography and etching remove the plate polysides from the rest of the memory cell arrays. The coupling ratio is increased by applying a voltage to the boosting plate formed by the method. At this time, due to the step of the transistor formed in the previous process, the plate polyside to be removed during the etching process increases on the side of the fin. In the etching process to remove a large number of plate polysides, the plate polyside and the oxide layer under the etch are etched to expose the silicon substrate in a portion where the plate polyside is thin because there is no step like the bit line contact and the common source line. The problem of etching is caused. Therefore, the thickness of the oxide film under the plate polyside must be increased. However, when the thickness of the oxide film is increased, the capacitance value of the oxide film is relatively decreased, and thus the role of the boosting plate is reduced, thereby increasing the thickness. This etching problem remains a process difficulty in producing the boost plate 쎌.
본 발명의 목적은 플레이트 폴리사이드 하부 산화막의 두께를 선택적으로 다르게 하여 후속공정중 플레이트 폴리사이드가 식각되는 부분에서는 산화막의 두께를 크게 하여 공정을 쉽게 진행할 수 있는 불휘발성 반도체 메모리 장치의 제조방법을 제공함에 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a nonvolatile semiconductor memory device in which the thickness of an oxide film under the plate polyside is selectively changed to increase the thickness of the oxide film in a portion where the plate polyside is etched during a subsequent process. Is in.
본 발명의 다른 목적은 쎌 어레이내에서는 산화막의 두께를 작게 하여 승압 플레이트의 역할을 최대한으로 살릴 수 있는 불휘발성 반도체 메모리 장치의 제조방법을 제공함에 있다.Another object of the present invention is to provide a method of manufacturing a nonvolatile semiconductor memory device capable of maximizing the role of a boosting plate by reducing the thickness of an oxide film in a fin array.
도 1은 본 발명의 일실시예에 따른 쎌 레이아웃도.1 is a layout diagram according to an embodiment of the present invention.
도 2a ∼ 도 2j는 도 1의 A-B 방향으로의 쎌 공정단면도들.2A to 2J are cross-sectional views of the step V in the direction A-B of FIG. 1.
상기한 목적들을 달성하기 위한 본 발명의 기술적 사상에 따르면, 활성 영역과 소자분리 영역이 일정 간격으로 배열되며, 플로팅 게이트에 전자주입 또는 전자방출로 데이터를 저장하는 메모리 쎌과, 이와 연결되어 이를 선택하는 선택 트랜지스터를 가지는 불휘발성 반도체 메모리 장치의 제조방법에 있어서, 실리콘 기판위에 소자분리영역과 터널 산화막을 형성하는 과정과, 제1도전체를 침적하고 제1사진 공정을 진행한 후 제1도전체를 식각하는 과정과, 상기 제1도전체 상부에 제1층간절연막을 형성하고 제2도전체를 침적하는 과정과, 제2사진 공정 진행 후 상기 제2도전체, 제1층간절연막 및 제1도전체를 연속적으로 식각하는 과정과, 제3사진 공정 진행 후 제3도전체가 식각될 영역에 한정하여 이온주입하는 과정과, 전면에 제2층간절연막을 형성하는 과정과, 상기 제3도전체를 침적하는 과정과, 제4사진 공정 진행 후 상기 제3도전체를 식각하는 과정을 포함함을 특징으로 한다.According to the technical idea of the present invention for achieving the above object, the active region and the device isolation region is arranged at regular intervals, and the memory 하는 for storing data by electron injection or electron emission in the floating gate, connected to this selected A method of manufacturing a nonvolatile semiconductor memory device having a select transistor, the method comprising: forming a device isolation region and a tunnel oxide film on a silicon substrate, depositing a first conductor, and then performing a first photographic process; Etching, forming a first interlayer insulating film on the first conductor, depositing a second conductor, and performing a second photolithography process, followed by the second conductor, the first interlayer insulating film, and the first conductive film. A process of continuously etching the sieve, a process of ion implantation limited to a region where the third conductor is to be etched after the third photo process is performed, and a second interlayer insulating film formed on the entire surface And depositing the third conductor and etching the third conductor after the fourth photo process.
이하 본 발명의 바람직한 실시예를 첨부한 도면을 참조하여 상세히 설명한다. 우선 각 도면의 구성요소들에 참조부호를 부가함에 있어서, 동일한 구성요소들에 한해서는 비록 다른 도면상에 표시되더라도 가능한한 동일한 부호를 가지도록 하고 있음에 유의해야 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. First, in adding reference numerals to the components of each drawing, it should be noted that the same reference numerals have the same reference numerals as much as possible even if displayed on different drawings.
도 1은 본 발명의 일실시예에 따른 쎌 레이아웃도이다. 도 1을 참조하면, 쎌 레이아웃은 두 개의 비트라인을 하나의 콘택에 연결시킨 공유 비트라인 구조를 나타내며 플레이트 산화막 이온주입이 행하여지는 구역을 선택 트랜지스터와 메모리 쎌 사이부터 콘택 주위 부분까지로 한정하고 있다.1 is a schematic layout diagram according to an embodiment of the present invention. Referring to FIG. 1, the X-ray layout shows a shared bit line structure in which two bit lines are connected to one contact, and a region in which plate oxide ion implantation is performed is defined between the select transistor and the memory pin from the portion around the contact. .
도 2a ∼ 도 2j는 도 1의 A-B 방향으로의 쎌 공정단면도들이다. 도 2a를 참조하면, 피형 단결정 실리콘 기판 100에 활성 영역과 분리를 위한 필드 산화막을 형성한 후 퍼니스(Furnace)에서 건식 산화로 90Å의 터널 산화막 10을 형성한다. 도 2b를 참조하면, 상기 공정 후 메모리 쎌의 플로팅 게이트를 형성할 1000Å의 제1폴리실리콘 20을 침적함과 동시에 POCL3를 도핑한 후 사진 공정과 식각 공정을 통하여 필드 산화막위의 제1폴리실리콘 20을 식각한다. 상기 공정후 포토레지스트를 제거하고 제1폴리실리콘 20 상부에 50Å의 산화막을 퍼니스에서 열산화 공정으로 형성하고 형성된 산화막위에 연속해서 저압 화학기상증착(LPCVD)을 이용하여 120Å의 질화막을 침적한다. 다음 퍼니스에서 1000℃, 습식 분위기에서 열산화공정으로 상기 질화막위에 50Å의 산화막을 형성한다. 이로써 플로팅 게이트와 콘트롤 게이트간 층간절연막인 산화막/질화막/산화막(Oxide Nitride Oxide: 이하 오엔오막이라 칭함) 30이 형성된다. 연속으로 제2폴리실리콘 40을 1000Å정도 침적 및 POCL3을 도핑한 후 1000Å의 텅스텐 실리사이드(WSix) 50를 침적한다. 도 2c를 참조하면, 상기 공정후 사진 공정을 통하여 쎌 어레이내에서 게이트가 될 부분을 포토레지스트 60a로 가리고 노출된 부분을 자기정합으로 텅스텐 실리사이드 50, 제2폴리실리콘 40, 오엔오막 30, 제1폴리실리콘 20을 연속으로 식각한다. 상기 공정 후 쎌 어레이내 소오스 또는 드레인들 15a ∼ 15e를 형성하는 이온주입을 실시한다. 도 2d를 참조하면, 상기 공정 후 사진 공정을 통하여 선택 트랜지스터와 메모리 쎌사이부터 콘택 주위의 부분까지를 제외한 나머지 부분을 포토레지스트 65로 가리고 고농도 비소(As+), 1E13∼1E/㎠, 50keV 조건으로 이온주입을 행하여 준다. 도 2e를 참조하면, 포토 레지스트 65를 제거한 후 퍼니스에서 산화공정을 통하여 300Å정도의 산화막 60b를 형성한다. 도 2f를 참조하면, 이때 후속 공정중에서 플레이트 폴리사이드가 식각되는 콘택 주위 부분 및 쎌 트랜지스터 및 선택 트랜지스터의 측벽에서는 이전 공정에서 상대적으로 고농도의 도펀트(Dopant)가 이온주입 및 POCL3 도핑이 되어 있으므로 쎌 어레이내보다 두꺼운 산화막이 형성된다. 폴리실리콘과 텅스텐 실리사이드를 연속으로 침적하여 플레이트 폴리사이드(plate polycide) 70을 형성한다. 도 2g를 참조하면, 사진공정을 통하여 콘택 주위부분의 플레이트 폴리사이드 70만을 노출시켜 식각시켜 준다. 이때 이전 공정에서 형성된 게이트의 단차에 의해서 실제적으로 침적한 플레이트 폴리사이드보다 더 두꺼운 폴리사이드를 식각해야 한다. 이러한 식각공정의 경우 폴리사이드 하부의 산화막은 실리콘 기판을 보호하며 만약 식각도중 산화막의 손실이 발생되어 실리콘 기판이 노출된다면 실리콘 기판이 식각되어 소자 기능이 저하된다. 전술한 바와 같은 본 발명에 따른 제조방법에서는, 쎌 어레이내에서는 기존의 300Å정도의 산화막을 유지하여 승압 플레이트의 역할을 극대화하는 동시에 플레이트 폴리사이드가 식각되는 부분에서는 상대적으로 두꺼운 산화막을 유지하고 있으므로 실리콘 기판 식각에 대한 마스킹 역할을 향상시킬 수 있다. 도 2h를 참조하면, 1000Å의 고온산화막을 침적하고 6000Å의 보로포스포 실리케이트 글래스(borophosphosilicate glass) 80을 침적한다. 도 2i를 참조하면, 다음 퍼니스에서 상기 보로포스포 실리케이트 글래스 80을 리플로우(reflow)하여 평탄화하고 사진 및 식각 공정으로 콘택을 형성한다. 도 2j를 참조하면, 상기 공정후 300Å의 티타늄(Ti)과 400Å의 티타늄 질화막(TiN)을 침적하고 퍼니스에서 어닐링(Annealing)한 다음 6000Å의 알루미늄(aluminum)을 침적하고 다시 250Å정도의 티타늄 질화막을 침적한다. 사진 공정과 식각 공정으로 금속 라인 90을 패턴한다.2A to 2J are cross-sectional views of the process in the AB direction of FIG. 1. Referring to FIG. 2A, after forming a field oxide film for separation from an active region on a single-crystal silicon substrate 100, a tunnel oxide film 10 of 90 Å is formed by dry oxidation in a furnace. Referring to FIG. 2B, the first polysilicon on the field oxide layer is deposited through the photolithography process and the etching process after depositing the 1000 polysilicon first polysilicon 20 to form the floating gate of the memory fabric after the process and doping POCL 3 . Etch 20. After the above process, the photoresist is removed and a 50-kV oxide film is formed on the first polysilicon 20 by a thermal oxidation process in a furnace, and 120-kV nitride film is subsequently deposited on the formed oxide film by low pressure chemical vapor deposition (LPCVD). Next, an oxide film of 50 kPa is formed on the nitride film by thermal oxidation in a furnace at 1000 ° C. in a wet atmosphere. As a result, an oxide film / nitride film / oxide film 30, which is an interlayer insulating film between the floating gate and the control gate, is formed. Subsequently, the second polysilicon 40 is deposited about 1000 m 3 and doped with POCL 3 , followed by the deposition of 1000 m 2 of tungsten silicide (WSix) 50. Referring to FIG. 2C, through the photo process, the tungsten silicide 50, the second polysilicon 40, the ohio film 30, and the first part are covered by photoresist 60a, and the exposed portions are self-aligned in the array. Polysilicon 20 is etched continuously. After the above process, ion implantation is performed to form sources or drains 15a to 15e in the array. Referring to FIG. 2D, a photoresist process is performed to cover the remaining portions of the photoresist 65 except for the portion around the contact from the selection transistor and the memory 리고 under high concentration of arsenic (As +), 1E13 to 1E / cm 2, and 50 keV. Ion implantation is performed. Referring to FIG. 2E, after removing the photoresist 65, an oxide film 60b of about 300 kV is formed through an oxidation process in a furnace. Referring to FIG. 2F, in the subsequent process, the portion around the contact where the plate polyside is etched and the sidewalls of the 쎌 transistor and the select transistor have relatively high concentrations of dopants ion implanted and POCL3 doped in the previous process. An oxide film thicker than the inside is formed. Polysilicon and tungsten silicide are subsequently deposited to form plate polycide 70. Referring to FIG. 2G, only the plate polyside 70 of the contact circumference is exposed and etched through the photolithography process. At this time, the thicker polyside than the plate polyside actually deposited should be etched by the step difference of the gate formed in the previous process. In this etching process, the oxide layer under the polyside protects the silicon substrate. If the silicon substrate is exposed due to the loss of the oxide layer during etching, the silicon substrate is etched to degrade the device function. In the manufacturing method according to the present invention as described above, while maintaining the existing oxide film of about 300 kV in the fin array to maximize the role of the boost plate, while maintaining a relatively thick oxide film in the portion where the plate polyside is etched silicon The masking role for substrate etching can be improved. Referring to FIG. 2H, a 1000 mW high temperature oxide film is deposited and 6000 mV borophosphosilicate glass 80 is deposited. Referring to FIG. 2I, the Borophospho silicate glass 80 is reflowed and planarized in the next furnace to form contacts by photo and etching processes. Referring to FIG. 2J, after the process, 300 Å of titanium (Ti) and 400 티타늄 of titanium nitride (TiN) were deposited and annealed in the furnace, followed by deposition of 6000 알루미늄 of aluminum (aluminum). To be deposited. The metal line 90 is patterned by a photo process and an etching process.
상기한 본 발명에 따르면, 플레이트 폴리사이드 하부 산화막의 두께를 선택적으로 다르게 하여 후속공정중 플레이트 폴리사이드가 식각되는 부분에서는 산화막의 두께를 크게 하여 공정을 쉽게 진행할 수 있는 효과가 있으며, 쎌 어레이내에서는 산화막의 두께를 작게 하여 승압 플레이트의 역할을 최대한으로 살릴 수 있는 효과가 있다.According to the present invention described above, the thickness of the lower portion of the plate polyside is selectively changed to increase the thickness of the oxide layer in the portion where the plate polyside is etched during the subsequent process, so that the process can be easily performed. By reducing the thickness of the oxide film there is an effect that can maximize the role of the boost plate.
상기한 본 발명은 도면을 중심으로 예를들어 한정되었지만, 그 동일한 것은 본 발명의 기술적 사상을 벗어나지 않는 범위내에서 여러가지 변화와 변형이 가능함이 본 분야의 숙련된 자에게 있어 명백할 것이다.Although the present invention described above has been limited to, for example, the drawings, the same will be apparent to those skilled in the art that various changes and modifications can be made without departing from the technical spirit of the present invention.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970011070A KR19980075019A (en) | 1997-03-28 | 1997-03-28 | Method of manufacturing nonvolatile semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970011070A KR19980075019A (en) | 1997-03-28 | 1997-03-28 | Method of manufacturing nonvolatile semiconductor memory device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR19980075019A true KR19980075019A (en) | 1998-11-05 |
Family
ID=65951056
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019970011070A KR19980075019A (en) | 1997-03-28 | 1997-03-28 | Method of manufacturing nonvolatile semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR19980075019A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030043737A (en) * | 2001-11-26 | 2003-06-02 | 가부시키가이샤 히타치세이사쿠쇼 | Substrate apparatus and producting method |
-
1997
- 1997-03-28 KR KR1019970011070A patent/KR19980075019A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030043737A (en) * | 2001-11-26 | 2003-06-02 | 가부시키가이샤 히타치세이사쿠쇼 | Substrate apparatus and producting method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2670219B2 (en) | Method of manufacturing nonvolatile semiconductor memory device | |
| US6376876B1 (en) | NAND-type flash memory devices and methods of fabricating the same | |
| US6197639B1 (en) | Method for manufacturing NOR-type flash memory device | |
| US6706594B2 (en) | Optimized flash memory cell | |
| JP3625661B2 (en) | Nonvolatile memory device and operation method thereof | |
| US6204122B1 (en) | Methods of forming nonvolatile integrated circuit memory devices having high capacitive coupling ratios | |
| KR0161402B1 (en) | Method of manufacturing non-volatile memory | |
| US5960285A (en) | Flash EEPROM device | |
| KR19990075948A (en) | Method for manufacturing non-volatile memory device using self-aligned source process | |
| KR100275746B1 (en) | Nonvolatile memory device fabrication method for protecting stacked gate side wall and active region | |
| KR19990080091A (en) | Nonvolatile Memory Device and Manufacturing Method Thereof | |
| KR100275735B1 (en) | Method for manufacturing nor-type flash memory device | |
| US7041555B2 (en) | Method for manufacturing flash memory device | |
| US6277693B1 (en) | Self-aligned process for forming source line of ETOX flash memory | |
| US6417048B1 (en) | Method for fabricating flash memory with recessed floating gates | |
| KR19980075019A (en) | Method of manufacturing nonvolatile semiconductor memory device | |
| KR930008081B1 (en) | Single poly eeprom cell and method for fabricating thereof | |
| US6194271B1 (en) | Method for fabricating flash memory | |
| KR100285755B1 (en) | Non-volatile semiconductor memory device | |
| JP3949749B2 (en) | Flash memory device and manufacturing method thereof | |
| US20010004330A1 (en) | Non-volatile semiconductor memory device and manufacturing method thereof | |
| KR940009645B1 (en) | Manufacturing method of non-volatile memory device | |
| KR20010060038A (en) | Method for manufacturing dram cell capacitor | |
| JP2616546B2 (en) | Manufacturing method of nonvolatile semiconductor memory device | |
| US20040065928A1 (en) | UV-programmed P-type mask ROM and fabrication thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WITN | Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid |