KR970072302A - Method for forming field oxide film of semiconductor device - Google Patents

Method for forming field oxide film of semiconductor device Download PDF

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Publication number
KR970072302A
KR970072302A KR1019960012724A KR19960012724A KR970072302A KR 970072302 A KR970072302 A KR 970072302A KR 1019960012724 A KR1019960012724 A KR 1019960012724A KR 19960012724 A KR19960012724 A KR 19960012724A KR 970072302 A KR970072302 A KR 970072302A
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South Korea
Prior art keywords
trench
oxide film
forming
semiconductor device
film
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KR1019960012724A
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Korean (ko)
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KR100192181B1 (en
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박상훈
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김주용
현대전자산업 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials

Abstract

본 발명은 반도체 소자의 필드 산화막 제조방법에 관한 것으로, 보다 구체적으로는 필드 산화막의 필드 인버젼을 방지할 수 있는 반도체 소자의 필드 산화막 형성방법에 관한 것이다. 본 발명에 따르면, 반도체 소자에 트렌치를 형성하고, 트렌치 하부에 채널 스톱퍼 확산 방지 이온을 주입한 다음, 필드 산화막을 형성하므로써, 채널 스톱퍼 불순물의 고온 공정으로 인화 외부 확산을 방지할 수 있으며, 평탄화되고, 버즈 빅이 없는 필드 산화막을 형성할 수 있다.Field of the Invention [0002] The present invention relates to a method of fabricating a field oxide film of a semiconductor device, and more particularly, to a field oxide film formation method of a semiconductor device capable of preventing a field inversion of a field oxide film. According to the present invention, a trench is formed in a semiconductor device, a channel stopper diffusion preventing ions are implanted into a lower portion of the trench, and a field oxide film is formed, thereby preventing external diffusion of print impurities in a high temperature process. , It is possible to form a field oxide film without burrs.

Description

반도체 소자의 필드 산화막 형성방법Method for forming field oxide film of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제2A도 내지 제2G도는 본 발명의 일실시예에 따른 반도체 소자의 필드 산화막 형성방법을 설명하기 위한 각 제조 공정을 나타낸 단면도2A to 2G are cross-sectional views illustrating respective manufacturing processes for explaining a field oxide film forming method of a semiconductor device according to an embodiment of the present invention

Claims (11)

반도체 기판에 패드 산화막과, 질화막 패턴을 형성하고, 질화막 패턴의 형태로 패드 산화막과 반도체 기판을 소정 깊이로 식각하여 제1트렌치를 형성하는 단계; 제1트렌치의 하부 영역에 확산 방지 이온을 주입하는 단계; 제1트렌치 부분을 단결정 에피택셜 성장시키는 단계; 상기 질화막 패턴 및 패드 산화막 및 양측벽 스페이서를 형성하는 단계; 상기 질화막 패턴, 패드 산화막 및 양측벽의 질화막 스페이서의 형태로 노출된 단결정 에피택셜층을 일정 깊이로 식각하여 제2트렌치를 형성하는 단계; 제2트렌치 내부에 채널 스톱불순물을 이온 주입하는 단계; 제2트렌치의 노출된 영역을 산화시키는 단계; 질화막 패턴, 질화막 스페이서 및 패드 산화막을 제거하는 단계; 및 산화가 이루어진 제2트렌치 내부에 산화 절연막을 매립시키는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 필드 산화막 형성방법.Forming a pad oxide film and a nitride film pattern on a semiconductor substrate and etching the pad oxide film and the semiconductor substrate to a predetermined depth in the form of a nitride film pattern to form a first trench; Implanting diffusion preventing ions into a lower region of the first trench; Single crystal epitaxial growth of the first trench portion; Forming a nitride film pattern, a pad oxide film, and both side wall spacers; Forming a second trench by etching a single crystal epitaxial layer exposed in the form of the nitride film pattern, the pad oxide film, and the nitride film spacers on both sides to a predetermined depth; Implanting a channel stop impurity into the second trench; Oxidizing the exposed region of the second trench; Removing the nitride film pattern, the nitride film spacer, and the pad oxide film; And burying an oxide insulating film in the second trench where oxidation is performed. 제1항에 있어서, 상기 제1트렌치의 깊이는 7000 내지 12000A인 것을 특징으로 하는 반도체 소자의 필드 산화막 형성방법.The method according to claim 1, wherein the depth of the first trench is 7000 to 12000A. 제1항에 있어서, 상기 확산 방지 이온은 산소 원자인 것을 특징으로 하는 반도체 소자의 필드 산화막 형성방법.The method of forming a field oxide film of a semiconductor device according to claim 1, wherein the diffusion preventing ions are oxygen atoms. 제1항에 있어서, 상기 확산 방지 이온은 1×1012내지 1×1018원자/㎤의 농도와, 20 내지 30KeV의 에너지 범위로 이온 주입하는 것을 특징으로 하는 반도체 소자의 필드 산화막 형성방법.The method according to claim 1, wherein the diffusion preventing ions are implanted at a concentration of 1 × 10 12 to 1 × 10 18 atoms / cm 3 and an energy range of 20 to 30 KeV. 제1항에 있어서, 상기 단결정 에피택셜 실리콘은 SiH2CI2가스에 의하여 형성하는 것을 특징으로 하는 반도체 소자의 필드 산화막 형성방법.The method of forming a field oxide film of a semiconductor device according to claim 1, wherein the single crystal epitaxial silicon is formed by SiH 2 CI 2 gas. 제1항에 있어서, 상기 채널 스톱 불순물로는 B 또는 BF3불순물로 1×1011내지 1×1015원자/㎤의 농도와 15 내지 30KeV의 에너지 범위로 이온 주입하는 것을 특징으로 하는 반도체 소자의 필드 산화막 형성방법.The semiconductor device according to claim 1, wherein the channel stop impurity is ion-implanted at a concentration of 1 × 10 11 to 1 × 10 15 atoms / cm 3 and an energy range of 15 to 30 KeV as a B or BF 3 impurity Field oxide film forming method. 제1항에 있어서, 상기 제2트렌치의 노출된 영역은 2000 내지 4000A 두께로 산화시키는 것을 특징으로 하는 반도체 소자의 필드 산화막 형성방법.The method as claimed in claim 1, wherein the exposed region of the second trench is oxidized to a thickness of 2000 to 4000 A. 제1항에 있어서, 상기 제2트렌치 영역을 매립시키는 산화 절연막은 TEOS 막인 것을 특징으로 하는 반도체 소자의 필드 산화막 형성방법.The method according to claim 1, wherein the oxide insulating film for embedding the second trench region is a TEOS film. 제8항에 있어서, 상기 TEOS 산화막의 두께는 5000 내지10000A인 것을 특징으로 하는 반도체 소자의 필드 산화막 형성방법.9. The method according to claim 8, wherein the thickness of the TEOS oxide film is 5000 to 10000A. 제1항에 있어서, 상기 산화 절연막을 제2트렌치내에 매립시키는 방법은 에치백 방법에 의하여 매립시키는 것을 특징으로 하는 반도체 소자의 필드 산화막 형성방법.The method of forming a field oxide film of a semiconductor device according to claim 1, wherein the method of embedding the oxide insulating film in the second trench is performed by an etch-back method. 제1항에 있어서, 상기 산화 절연막을 제2트렌치내에 매립시키는 방법은 CMP 방법에 의하여 매립시키는 것을 특징으로 하는 반도체 소자의 필드 산화막 형성방법.The method of forming a field oxide film of a semiconductor device according to claim 1, wherein the method of embedding the oxide insulating film in the second trench is performed by a CMP method. ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960012724A 1996-04-24 1996-04-24 Method of forming field oxide film in a semiconductor device KR100192181B1 (en)

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