KR100192181B1 - Method of forming field oxide film in a semiconductor device - Google Patents
Method of forming field oxide film in a semiconductor device Download PDFInfo
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- KR100192181B1 KR100192181B1 KR1019960012724A KR19960012724A KR100192181B1 KR 100192181 B1 KR100192181 B1 KR 100192181B1 KR 1019960012724 A KR1019960012724 A KR 1019960012724A KR 19960012724 A KR19960012724 A KR 19960012724A KR 100192181 B1 KR100192181 B1 KR 100192181B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 238000000034 method Methods 0.000 title claims abstract description 30
- 239000012535 impurity Substances 0.000 claims abstract description 12
- 150000002500 ions Chemical class 0.000 claims abstract description 10
- 238000009792 diffusion process Methods 0.000 claims abstract description 9
- 150000004767 nitrides Chemical class 0.000 claims description 27
- 239000000758 substrate Substances 0.000 claims description 12
- 125000006850 spacer group Chemical group 0.000 claims description 11
- 239000013078 crystal Substances 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 125000004430 oxygen atom Chemical group O* 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 4
- 125000004429 atom Chemical group 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 239000007789 gas Substances 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000001684 chronic effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
- H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- Manufacturing & Machinery (AREA)
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- Formation Of Insulating Films (AREA)
Abstract
본 발명은 반도체 소자의 필드 산화막 제조방법에 관한 것으로, 보다 구체적으로는 필드 산화막의 필드 인버젼을 방지할 수 있는 반도체 소자의 필드 산화막 형성방법에 관한 것이다. 본 발명에 따르면, 반도체 소자에 트렌치를 형성하고, 트렌치 하부에 채널 스톱퍼 확산 방지 이온을 주입한 다음, 필드 산화막을 형성하므로써, 채널 스톱퍼 불순물의 고온 공정으로 인한 외부 확산을 방지할 수 있으며, 평화되고, 버즈 빅이 없는 필드 산화막을 형성할 수 있다.The present invention relates to a method for producing a field oxide film of a semiconductor device, and more particularly, to a method of forming a field oxide film of a semiconductor device capable of preventing field inversion of a field oxide film. According to the present invention, by forming a trench in the semiconductor device, implanting channel stopper diffusion preventing ions into the trench, and then forming a field oxide film, it is possible to prevent external diffusion due to the high temperature process of the channel stopper impurities, It is possible to form a field oxide film without buzz big.
Description
제1도는 종래의 방법에 따른 반도체 소자의 필드 산화막 형성방법을 보인 단면도.1 is a cross-sectional view showing a method for forming a field oxide film of a semiconductor device according to a conventional method.
제2도(a) 내지 제2도(g)는 본 발명의 일실시예에 따른 반도체 소자의 필드 산화막 형성방법을 설명하기 위한 각 제조 공정을 나타낸 단면도.2A to 2G are cross-sectional views showing respective manufacturing processes for explaining a method of forming a field oxide film of a semiconductor device according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 반도체 기판 12 : 패드 산화막11 semiconductor substrate 12 pad oxide film
14 : 폴리실리콘막 15 : 질화막14 polysilicon film 15 nitride film
16 : 스페이서 17 : 채널 스톱퍼층16 spacer 17 channel stopper layer
18 : 액상 산화막 19 : 이중의 필드 산화막18 liquid oxide film 19 double field oxide film
20 : 트랜치 100 : 채널 스톱퍼층20: trench 100: channel stopper layer
[발명의 기술분야]Technical Field of the Invention
본 발명은 반도체 소자의 필드 산화막 제조방법에 관한 것으로, 보다 구체적으로는 필드 산화막의 인버젼(field inversion)을 방지할 수 있는 반도체 소자의 필드 산화막 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for producing a field oxide film of a semiconductor device, and more particularly to a method of forming a field oxide film of a semiconductor device capable of preventing field inversion of a field oxide film.
[종래 기술][Prior art]
현재의 반도체 소자는 고집적화됨에 따라 소자의 활성 영역의 면적 밀도가 증가하고 있다. 이러한 활성 영역의 면적 밀도는 소자의 분리 영역의 면적에 의하여 결정된다. 일반적으로 공지된 반도체 소자의 분리 기술은 로코스 기술로써, 국부적으로 선택적 산화를 이루어 필드 산화막을 형성하여 소자간의 절연특성을 확보하였다.As the current semiconductor devices are highly integrated, the area density of the active regions of the devices increases. The area density of this active region is determined by the area of the isolation region of the device. In general, a known technology of semiconductor device separation is a LOCOS technology, and locally selective oxidation is performed to form a field oxide film, thereby securing insulation characteristics between devices.
종래에는 제1도에 도시된 바와 같이, 로코스에 의한 문제점을 개선하기 위하여 패드 산화막과 질화막 사이에 완충용 폴리실리콘을 개재한 PBLOCOS(poly buffered LOCOS) 방법이 제안되었다.Conventionally, as shown in FIG. 1, in order to improve the problem caused by LOCOS, a PBLOCOS (poly buffered LOCOS) method having a buffer polysilicon interposed between a pad oxide film and a nitride film has been proposed.
여기서, 종래의 필드 산화막의 형성방법을 살펴보면, 제1도에 도시된 바와 같이, 반도체 기판(1) 상부에 50 내지 150Å의 두께를 지니는 패드 산화막(2)이 형성되고, 그 상부에 실리콘 질화막(3)이 순차적으로 형성된다.Here, referring to a conventional method of forming a field oxide film, as shown in FIG. 1, a pad oxide film 2 having a thickness of 50 to 150 GPa is formed on a semiconductor substrate 1, and a silicon nitride film ( 3) are formed sequentially.
이어서, 필드 산화막 예정 부위가 노출되도록, 감광막 패턴(도시되지 않음)이 형성되고, 이 감광막 패턴(도시되지 않음)에 따라, 질화막(3)이 식각된다. 그리고 난 다음, 노출된 반도체 기판 면에 불순물이 이온 주입되어, 채널 스톱퍼층(5)이 형성된다. 이 채널 스톱퍼층(5)은 활성 영역과 이와 이웃하는 다른 활성 영역을 전기적으로 분리시켜 소자의 동작시 높은 전위 장벽을 형성하기 위하여, 반도체 기판과 동일한 타입의 불순물이 고농도로 주입된다. 그런 다음, 감광막 패턴이 제거되고, 이상의 결과물을 고온에서 열산화함으로써, 필드 산화막(6)이 형성된다.Subsequently, a photosensitive film pattern (not shown) is formed so that the field oxide film predetermined portion is exposed, and the nitride film 3 is etched according to the photosensitive film pattern (not shown). Then, impurities are implanted into the exposed surface of the semiconductor substrate to form the channel stopper layer 5. The channel stopper layer 5 is implanted at a high concentration with impurities of the same type as the semiconductor substrate in order to electrically separate the active region from the other active regions adjacent thereto to form a high potential barrier during operation of the device. Then, the photosensitive film pattern is removed, and the field oxide film 6 is formed by thermally oxidizing the above result at a high temperature.
[발명이 이루고자 하는 기술적 과제][Technical problem to be achieved]
그러나, 로코스 기술에 의하여 형성된 필드 산화막은 국부 성장시 성장 저지막으로 이용되는 질화막 하부에 산화막이 침투하여 버즈 빅(bird's beak)이라는 고질적인 문제점을 지니고 있으며, 또한, 열산화 공정시, 필드 산화막 예정 부위에 이온 주입된 채널 스톱퍼 불순물이 외부로 확산되어, 채널 스톱퍼 영역(5)은 저농도 상태가 된다. 이로 인하여, 소자의 동작시 채널 스톱퍼 영역이 저농도인 이유로 필드 인버젼이 발생되고, 필드 산화막 하부 영역에는 쉽게 채널이 형성되어, 다른 활성 영역과 용이하게 전기적 턴온이 발생하는 문제점이 발생하였다.However, the field oxide film formed by the LOCOS technique has a chronic problem of bird's beak due to the penetration of an oxide film under the nitride film used as a growth barrier film during local growth, and a field oxide film during the thermal oxidation process. The channel stopper impurity ion-implanted in the predetermined site diffuses to the outside, and the channel stopper region 5 is in a low concentration state. As a result, field inversion occurs due to the low concentration of the channel stopper region during the operation of the device, and a channel is easily formed in the lower region of the field oxide layer, thereby easily causing electrical turn-on with other active regions.
따라서, 본 발명의 상기한 종래의 문제점을 해결하기 위한 것으로, 필드 산화막 형성시, 버즈 빅 현상을 방지함과 동시에 채널 스톱퍼 불순물의 외부 확산을 방지하여, 인접한 다른 활성 영역간의 전기적 도통을 방지하여 필드 산화막의 절연 특성 및 소자의 신뢰성을 향상시킬 수 있는 반도체 소자의 필드 산화막 형성방법을 제공하는 것을 목적으로 한다.Therefore, to solve the above-mentioned problems of the present invention, the field oxide film is formed, preventing the buzz big phenomenon and at the same time prevent the external diffusion of the channel stopper impurities, and prevent the electrical conduction between adjacent active regions It is an object of the present invention to provide a method for forming a field oxide film of a semiconductor device capable of improving the insulating properties of the oxide film and the reliability of the device.
[발명의 구성 및 작용][Configuration and Function of Invention]
상기한 본 발명의 목적을 달성하기 위하여, 본 발명은, 반도체 기판에 패드 산화막과, 질화막 패턴을 형성하고, 질화막 패턴의 형태로 패드 산화막과 반도체 기판을 소정 깊이로 식각하여 제1트렌치를 형성하는 단계; 제1트렌치의 하부 영역에 확산 방지 이온을 주입하는 단계; 제1트랜치 부분을 단결정 에피택셜 성장시키는 단계; 상기 질화막 패턴 및 패드 산화막 양측벽에 질화막 스페이서를 형성하는 단계; 상기 질화막 패턴, 패드 산화막 및 양측벽의 질화막 스페이서의 형태로 노출된 단결정 에피택셜층을 일정 깊이로 식각하여 제2트렌치를 형성하는 단계; 제2트렌치 내부에 채널 스톱 불순물을 이온 주입하는 단계; 제2트렌치의 노출된 영역을 산화시키는 단계; 질화막 패턴, 질화막 스페이서 및 패드 산화막을 제거하는 단계; 및 산화가 이루어진 제2트렌치 내부에 산화 절연막을 매립시키는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object of the present invention, the present invention is to form a pad oxide film and a nitride film pattern on a semiconductor substrate, and to form a first trench by etching the pad oxide film and the semiconductor substrate to a predetermined depth in the form of a nitride film pattern. step; Implanting diffusion preventing ions into the lower region of the first trench; Epitaxially growing the first trench portions; Forming a nitride film spacer on both sides of the nitride film pattern and the pad oxide film; Forming a second trench by etching the single crystal epitaxial layer exposed in the form of the nitride layer pattern, the pad oxide layer, and the nitride layer spacers on both sidewalls to a predetermined depth; Ion implanting channel stop impurities into the second trench; Oxidizing the exposed region of the second trench; Removing the nitride film pattern, the nitride film spacer, and the pad oxide film; And embedding an oxide insulating layer in the second trench in which the oxidation is performed.
이와 같이, 본 발명에 의하면, 인접한 다른 활성영역간의 전기적 도통을 방지하고, 필드 산화막의 절연 특성 및 소자의 신뢰성을 향상시킬 수 있다.As described above, according to the present invention, it is possible to prevent electrical conduction between adjacent active regions and to improve the insulation characteristics of the field oxide film and the reliability of the device.
[실시예]EXAMPLE
이하, 본 발명의 바람직한 실시예를 첨부한 도면에 의거하여 자세히 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
첨부한 도면 제1도(a) 내지 제2도(g)는 본 발명에 따른 반도체 소자의 필드 산화막 제조방법을 설명하기 위한 각 제조공정을 나타낸 단면도이다.1A to 2G are cross-sectional views showing respective manufacturing steps for explaining a method for manufacturing a field oxide film of a semiconductor device according to the present invention.
먼저, 제1도(a)에 도시된 바와 같이, 반도체 기판(11)에 패드 산화막(12)이 열산화 방법에 의하여 100 내지 200Å 두께로 형성되고, 그 상부에 질화막 패턴(13)이 1000 내지 2500Å 두께로 형성된다.First, as shown in FIG. 1A, a pad oxide film 12 is formed on the semiconductor substrate 11 to a thickness of 100 to 200 microseconds by a thermal oxidation method, and a nitride film pattern 13 is formed on the upper surface of the semiconductor substrate 11. It is formed to a thickness of 2500Å.
제2도(b)는 그 이후 공정이 진행된 반도체 소자의 단면을 보인 것으로, 질화막 패턴(13)이 식각 마스크로 이용되어, 패드 산화막(12) 및 반도체 기판이 일정 깊이만큼 식각되어, 트렌치(14)가 형성된다. 이때, 트렌치(14)의 깊이는 약 7000 내지 12000Å이 되도록 식각됨이 바람직하고, 이어서, 트렌치 하단에 산소 원자(도면에서 +++로 표시)가 1×1012내지 1×1018원자/㎤의 농도와, 20 내지 30KeV의 에너지 범위로 이온 주입된다. 이때, 산소 원자(도면에서 +++로 표시됨)가 이온 주입되는 이유는 이후의 채널 스톱퍼 불순물들이 확산됨을 저지하기 위하여 주입된다.FIG. 2B is a cross-sectional view of the semiconductor device after which the process has been performed. The nitride film pattern 13 is used as an etching mask, and the pad oxide film 12 and the semiconductor substrate are etched by a predetermined depth to form a trench 14. ) Is formed. At this time, the depth of the trench 14 is preferably etched to be about 7000 to 12000 kPa, and then, at the lower end of the trench, an oxygen atom (denoted as +++ in the figure) is 1 × 10 12 to 1 × 10 18 atoms / cm 3. And ion implantation in the energy range of 20 to 30 KeV. At this time, the reason why the oxygen atom (indicated by +++ in the figure) is implanted is to prevent the subsequent channel stopper impurities from diffusing.
트렌치(14)가 단결정 에피택셜 실리콘막(15)으로 매립된 단면이 제2도(c)에 도시되어 있다. 이때, 단결정 에피택셜 실리콘막(15)은 SiH2Cl2가스에 의하여 저압 공정으로 형성된다.(SiH2Cl2→SiCl2+ H2→Si + 2HCl)A cross section in which the trench 14 is embedded with the single crystal epitaxial silicon film 15 is shown in FIG. At this time, the single crystal epitaxial silicon film 15 is formed by a low pressure process by SiH 2 Cl 2 gas (SiH 2 Cl 2 → SiCl 2 + H 2 → Si + 2HCl).
제2도(d)에 도시된 바와 같이, 패드 산화막(12)과 질화막 패턴(13)의 양측벽에 블랭킷 식각 방식에 의하여 스페이서(16)가 형성된다. 이때, 스페이서(16)는 단결정 에피택셜 실리콘막(15)과 식각비 차이가 나는 물질로 형성됨이 바람직하고, 더욱 바람직하게는, 질화막으로 이루어진다.As shown in FIG. 2D, spacers 16 are formed on both sidewalls of the pad oxide layer 12 and the nitride layer pattern 13 by a blanket etching method. In this case, the spacer 16 is preferably formed of a material having an etch ratio difference from that of the single crystal epitaxial silicon film 15, and more preferably, a nitride film.
제2도(e)에 도시된 바와 같이, 질화막 패턴(13)과 스페이서(16)에 의하여 노출된 단결정 에피택셜 실리콘막(15)이 비등방성 식각되어 제2트렌치(17)가 형성된다. 이때, 제2트렌치(17)는 산소 원자(도면에서 +++로 표시됨)가 이온 주입된 층이 노출되도록 식각됨이 바람직하다. 이어서, 제2트렌치(17)의 노출된 부분에 B 또는 BF3불순물이 1×1011내지 1×1015원자/㎤의 농도와, 15 내지 50KeV의 에너지 범위로 이온 주입되어, 채널 스톱퍼층(100)이 형성된다.As illustrated in FIG. 2E, the single crystal epitaxial silicon film 15 exposed by the nitride film pattern 13 and the spacer 16 is anisotropically etched to form a second trench 17. In this case, the second trench 17 is preferably etched to expose the layer implanted with oxygen atoms (indicated by +++ in the drawing). Subsequently, B or BF 3 impurities are ion implanted into the exposed portion of the second trench 17 at a concentration of 1 × 10 11 to 1 × 10 15 atoms / cm 3 and an energy range of 15 to 50 KeV, thereby providing a channel stopper layer ( 100) is formed.
그 다음에, 제2도(f)에 도시된 바와 같이, 노출된 제2트렌치 부분이 2000 내지 4000Å 두께로 열산화되어 필드 산화막(18)이 형성된다. 이때, 필드 산화막(18)은 제2트렌치 표면으로부터 외부를 향해 소정 크기만큼 연장된 위치에 있다. 또한, 산소 원자는 상기에서 설명한 바와 같이, 채널 스톱퍼 불순물 확산을 방지하는 역할을 한다.Then, as shown in FIG. 2 (f), the exposed second trench portion is thermally oxidized to a thickness of 2000 to 4000 kPa to form a field oxide film 18. At this time, the field oxide film 18 is in a position extending from the surface of the second trench to the outside by a predetermined size. In addition, the oxygen atom serves to prevent diffusion of channel stopper impurities, as described above.
이어서, 제2도(g)에 도시된 바와 같이, 반도체 기판 상부에 존재되어 있는 질화막 스페이서(16) 및 질화막 패턴(13)은 약 160 내지 180℃의 인산에 의하여 제거되고, 패드 산화막(12)은 불산에 의하여, 제거된다. 이어서, 결과물 상부에 TEOS 산화막(20)이 하부 결과물이 매립될 만큼의 두께 바람직하게는, 5000 내지 10000Å 두께로 증착되고, 이 TEOS막(20)을 에치백 또는 CMP(chemical mechanical polishing) 공정을 진행하여 트렌치 부위가 매립된다. 이로써 평탄하고, 버즈 빅이 존재하지 않는 필드 산화막(18,20)이 형성된다.Subsequently, as shown in FIG. 2G, the nitride film spacer 16 and the nitride film pattern 13 existing on the semiconductor substrate are removed by phosphoric acid at about 160 ° C. to 180 ° C., and the pad oxide film 12 is removed. Is removed by hydrofluoric acid. Subsequently, a TEOS oxide film 20 is deposited on top of the resultant material to a thickness such that the bottom product is buried, preferably 5000 to 10000 mm thick, and the TEOS film 20 is etched back or subjected to chemical mechanical polishing (CMP) process. The trench is then buried. As a result, field oxide films 18 and 20 that are flat and do not have buzz big are formed.
[발명의 효과][Effects of the Invention]
이와 같이, 본 발명에 다르면, 채널 스톱퍼 영역의 확산이 방지되어 필드 인버젼을 감소시키고, 반도체 활성 영역을 최대로 확장할 수 있다.As described above, according to the present invention, diffusion of the channel stopper region can be prevented to reduce the field inversion and maximize the semiconductor active region.
Claims (11)
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019960012724A KR100192181B1 (en) | 1996-04-24 | 1996-04-24 | Method of forming field oxide film in a semiconductor device |
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| KR1019960012724A KR100192181B1 (en) | 1996-04-24 | 1996-04-24 | Method of forming field oxide film in a semiconductor device |
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