KR970072096A - Method for forming bonding pads of semiconductor devices - Google Patents

Method for forming bonding pads of semiconductor devices Download PDF

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Publication number
KR970072096A
KR970072096A KR1019960012726A KR19960012726A KR970072096A KR 970072096 A KR970072096 A KR 970072096A KR 1019960012726 A KR1019960012726 A KR 1019960012726A KR 19960012726 A KR19960012726 A KR 19960012726A KR 970072096 A KR970072096 A KR 970072096A
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KR
South Korea
Prior art keywords
film
forming
predetermined
metal wiring
protective film
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Application number
KR1019960012726A
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Korean (ko)
Inventor
김인철
Original Assignee
김주용
현대전자산업 주식회사
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019960012726A priority Critical patent/KR970072096A/en
Publication of KR970072096A publication Critical patent/KR970072096A/en

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  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 제조공정에서 와이어 본딩을 위한 본딩 패드 형성방법을 개시한다. 이 방법은 소정의 단위 셀 및 배선 등이 형성된 반도체 기판 상부에 소정의 층간 절연용 산화막이 형성된 반도체 소자에 있어서, 절연용 산화막 위에 소정 두께의 본딩 패드용 금속배선을 형성하는 단계; 금속배선 위에 보호막을 형성하는 단계; 보호막 위에 폴리이미드막을 형성하는 단계; 폴리이미드막의 소정부분을 노광과 현상공정을 통하여 보호막의 표면이 노출될 때까지 제거하는 단계; 노출된 보호막 표면을 소정의 에너지로서 O2플라즈마 식각하는 단계; 금속배선막의 표면이 노출될 때까지 소정의 에너지로서 플라즈마 식각하는 단계를 포함한다.The present invention discloses a method of forming a bonding pad for wire bonding in a manufacturing process of a semiconductor device. In this method, a predetermined interlayer insulating oxide film is formed on a semiconductor substrate on which predetermined unit cells and wirings are formed. The method includes the steps of: forming a metal wiring for a bonding pad having a predetermined thickness on an insulating oxide film; Forming a protective film on the metal wiring; Forming a polyimide film on the protective film; Removing a predetermined portion of the polyimide film through exposure and development until the surface of the protective film is exposed; O 2 plasma etching the exposed protective film surface with a predetermined energy; And plasma etching with predetermined energy until the surface of the metal wiring film is exposed.

Description

반도체 소자의 본딩 패드 형성방법Method for forming bonding pads of semiconductor devices

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제2도의 (가) 내지 (라)는 본 발명의 실시예에 따른 것으로서, 본딩 패드를 형성하기 위한 과정을 보여주는 공정 흐름도.FIG. 2 (a) through FIG. 2 (d) are process flow diagrams illustrating a process for forming a bonding pad according to an embodiment of the present invention;

Claims (6)

소정의 단위 셀 및 배선 등이 형성된 반도체 기판 상부에 소정의 층간 절연용 산화막이 형성된 반도체 소자에 있어서, 상기 산화막 위에 소정 두계의 본딩 패드용 금속배선을 형성하는 단계; 상기 금속배선 위에 보호막을 형성하는 단계; 보호막 위에 폴리이미드막을 형성하는 단계; 폴리이미드막의 소정부분을 노광과 현상 공정을 통하여 상기 보호막의 표면이 노출될 때까지 제거하는 단계; 노출된 보호막 표면을 소정의 에너지로서 O2프라즈마 식각하는 단계; 금속배선막의 표면이 노출될 때까지 소정의 에너지로서 플라즈마 식각하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 본딩패드 형성방법.A method of manufacturing a semiconductor device, comprising: forming a predetermined interlayer insulating oxide film on a semiconductor substrate on which predetermined unit cells and wirings are formed; Forming a protective film on the metal wiring; Forming a polyimide film on the protective film; Removing a predetermined portion of the polyimide film through exposure and development until the surface of the protective film is exposed; O 2 plasma etching the exposed protective film surface with a predetermined energy; And etching the metal wiring film with a predetermined energy until the surface of the metal wiring film is exposed. 제1항에 있어서, 상기 보호막은 하부의 산화막과, 상기 산화막 상부의 질화막으로 이루어지는 것을 특징으로 하는 반도체 소자의 본딩패드 형성방법.The method according to claim 1, wherein the protective film comprises a lower oxide film and a nitride film on the oxide film. 제1항에 있어서, 상기 폴리이미드막의 형성단계는 폴리이미드막의 코팅단계와, 코팅된 막의 큐어링단계를 포함하는 것을 특징으로 하는 반도체 소자의 본딩패드 형성방법.The method of claim 1, wherein the step of forming the polyimide film includes a step of coating the polyimide film and a step of curing the coated film. 제1항에 있어서, 상기 O2플라즈마 식각시 식각 두께는 5,000Å 이내인 것을 특징으로 하는 반도체 소자의 본딩패드 형성방법.The method of claim 1, wherein the etch thickness of the O 2 plasma etch is within 5,000 ANGSTROM. 제1항에 있어서, 상기 금속배선막의 표면을 노출시키기 위한 플라즈마 식각의 공급개스는 CF4, CHF3, O2및 Ar의 혼합개스인 것을 특징으로 하는 반도체 소자의 본딩패드 형성방법.The method according to claim 1, wherein the supply gas for plasma etching for exposing the surface of the metal wiring film is a mixed gas of CF 4 , CHF 3 , O 2, and Ar. 제2항 또는 제5항에 있어서, 상기 산화막과 질화막은 인시튜방식에 의하여 동시에 식각되는 것을 특징으로 하는 반도체 소자의 본딩패드 형성방법.The method of claim 2 or 5, wherein the oxide film and the nitride film are simultaneously etched by an in-situ process. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960012726A 1996-04-24 1996-04-24 Method for forming bonding pads of semiconductor devices KR970072096A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960012726A KR970072096A (en) 1996-04-24 1996-04-24 Method for forming bonding pads of semiconductor devices

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KR1019960012726A KR970072096A (en) 1996-04-24 1996-04-24 Method for forming bonding pads of semiconductor devices

Publications (1)

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KR970072096A true KR970072096A (en) 1997-11-07

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