KR970068325A - UTOPIA transmission access device of ATM adapter - Google Patents

UTOPIA transmission access device of ATM adapter Download PDF

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Publication number
KR970068325A
KR970068325A KR1019960007970A KR19960007970A KR970068325A KR 970068325 A KR970068325 A KR 970068325A KR 1019960007970 A KR1019960007970 A KR 1019960007970A KR 19960007970 A KR19960007970 A KR 19960007970A KR 970068325 A KR970068325 A KR 970068325A
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KR
South Korea
Prior art keywords
transmission
byte
data
signal
control signal
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KR1019960007970A
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Korean (ko)
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KR100212831B1 (en
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조상훈
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배순훈
대우전자 주식회사
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/20—Support for services
    • H04L49/208—Port mirroring
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9057—Arrangements for supporting packet reassembly or resequencing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/5652—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly

Abstract

본 발명은 ATM어답터의 SAR계층과 물리계층을 UTOPIA방식으로 접속하기 위한 장치에 관한 것으로, 바이트 단위의 데이타를 송신인에이블(/TxEnb)신호와 송신클럭(TxClk)에 따라 입력받아 저장함과 아울러 엠프티 플래그(Empty flag)정보를 제공하고, 바이트단위로 데이타를 출력하는 송신속도 정합버퍼(51); 송신속도 정합버퍼의 출력 데이타를 일시 지연시키기 위한 송신 데이타 버퍼(52); CRC제어신호에 따라 4바이트 헤더정보를 입력받아 CRC연산하여 헤더에러검사(HEC) 데이타를 발생하는 HEC 발생기(53); 선택제어신호에 따라 ATM 셀 시작으로 부터 4번째 바이트까지는 상기 데이타 버퍼의 출력을 선택하고, 이어서 5번째 바이트는 상기 HEC 발생기의 출력을 선택한 후 여섯번째 바이트로부터 53번째 바이트까지는 다시 상기 데이타 버퍼의 출력을 선택하여 ATM 셀 데이타를 바이트단위로 순차적으로 출력하는 선택수단; 송신클럭을 소정 수 카운터하여 이벤트신호를 발생하는 이벤트카운터; 및 송신셀 시작(TxSOC)신호와, 상기 이벤트 카운터의 출력, 상기 앰프티 플래그를 입력받아 상기 리드버퍼(/rd_fifo)신호와 상기 CRC제어신호와 상기 선택제어신호 및 스트로브(STRB)신호를 발생하여 송신 접속기능을 제어하는 송신 제어신호 발생기로 구성되어 회로 설계가 간단하고 동작이 안정되게 하는 효과가 있다.[0001] The present invention relates to an apparatus for connecting a SAR layer and a physical layer of an ATM adapter in a UTOPIA manner, and is configured to receive and store data in byte units according to a transmission enable (/ TxEnb) signal and a transmission clock (TxClk) A transmission rate matching buffer 51 for providing information on an empty flag and outputting data on a byte-by-byte basis; A transmission data buffer (52) for temporarily delaying output data of the transmission rate matching buffer; A HEC generator 53 for receiving 4-byte header information according to a CRC control signal and performing CRC calculation to generate header error check (HEC) data; The output of the data buffer is selected from the ATM cell start to the 4th byte according to the selection control signal, and the 5th byte selects the output of the HEC generator and then the output of the data buffer Selecting means for sequentially outputting ATM cell data on a byte-by-byte basis; An event counter for counting a predetermined number of transmission clocks and generating an event signal; (Rd_fifo) signal, the CRC control signal, the selection control signal, and the strobe (STRB) signal by receiving a transmission cell start (TxSOC) signal, an output of the event counter, And a transmission control signal generator for controlling the transmission connection function, so that the circuit design is simple and the operation is stable.

Description

ATM어답터의 유토피아(UTOPIA) 송신접속장치UTOPIA transmission access device of ATM adapter

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제3도는 본 발명에 따른 UTOPIA 송신접속장치를 도시한 블럭도.FIG. 3 is a block diagram showing a UTOPIA transmission access device according to the present invention; FIG.

Claims (4)

분할 및 조립(SAR)칩과 물리계층칩으로 분리되어 구현된 ATM 어답퍼에서 유토피아(UTOPIA) 접속기능이 없는 물리계층칩을 상기 분할 및 조립(SAR)칩에 접속하기 위하여 상기 분할 및 조립(SAR)칩으로 부터 물리계층칩으로의 유토피아(UTOPIA) 송신접속장치와 물리계층칩으로부너 분할 및 조립(SAR)칩으로의 유토피아(UTOPIA) 수신접속장치가 구비된 유토피아(UTOPIA) 접속 장치에 있어서, 상기 유토피아 (UTOPIA) 송신접속장치가, 상기 분할 및 조립(SAR)칩으로부터 바이트 단위의 데이타를 송신인에이블(/TxEnb)신호와 송신클럭(TxClk)에 따라 입력받아 저장함과 아울러 엠프티 플래그(Empty flag)정보를 제공하고, 리드버퍼(/rd_fifo)신호에 의해 바이트단위로 데이타를 출력하는 송신속도 정합버퍼(51); 상기 송신속도 정합버퍼의 출력 데이타를 일시 지연시키기 위한 송신 데이타 버퍼(52); CRC제어신호에 따라 송신속도 정합버퍼로부터 4바이트 헤더정보를 입력받아 CRC연산하여 헤더에러검사 (HEC) 데이타를 발생하는 헤더에러검사HEC 발생기(53); 선택제어신호에 따라 ATM 셀 시작으로 부터 4번째 바이트까지는 상기 데이타 버퍼의 출력을 선택하고, 이어서 5번째 바이트는 상기 헤더에러검사(HEC) 발생기의 출력을 선택한 후 여섯번째 바이트로부터 53번째 바이트까지는 다시 상기 데이타 버퍼의 출력을 선택하여 ATM 셀 데이타를 바이트단위로 순차적으로 출력하는 선택수단; 송신클럭을 소정 수 카운터하여 이벤트신호를 발생하는 이벤트카운터(55); 및 송신셀 시작(TxSOC)신호와, 상기 이벤트 카운터의 출력, 상기 앰프티 플래그를 입력받아 상기 송신속도 정합버퍼를 읽기 위한 상기 리드버퍼(/rd_fifo)신호와 상기 헤더에러검사(CRC) 발생기를 제어하기 위한 상기 CRC제어신호와 상기 선택수단을 제어하기 위한 상기 선택 제어신호 및 스트로브(STRB)신호를 발생하여 송신 접속기능을 제어하는 송신 제어신호 발생기(56)가 구비된 ATM 어답터의 유토피아(UTOPIA) 송신접속장치.(SAR) chip to connect a physical layer chip with no UTOPIA connection capability to the segmentation and assembly (SAR) chip in an ATM attacher implemented separately into a chip, a segmentation and assembly (SAR) chip and a physical layer chip, (UTOPIA) connection device having a UTOPIA transmission connection device from a chip to a physical layer chip and a UTOPIA reception connection device from a physical layer chip to a wobble division and assembly (SAR) chip, The UTOPIA transmission access device receives and stores byte-based data from the segmentation and assembly chip according to a transmission enable (/ TxEnb) signal and a transmission clock (TxClk), and stores an empty flag a transmission rate matching buffer 51 for providing flag information and outputting data in units of bytes by a read buffer (/ rd_fifo) signal; A transmission data buffer (52) for temporarily delaying output data of the transmission rate matching buffer; A header error check HEC generator 53 for receiving 4-byte header information from the transmission rate matching buffer according to the CRC control signal and performing CRC calculation to generate header error check (HEC) data; The output of the data buffer is selected from the beginning of the ATM cell to the 4th byte according to the selection control signal, and the 5th byte is selected again from the 6th byte to the 53rd byte after selecting the output of the header error checking (HEC) Selection means for selecting an output of the data buffer and outputting the ATM cell data sequentially in units of bytes; An event counter 55 for counting a predetermined number of transmission clocks and generating an event signal; (Rd_fifo) signal and a header error check (CRC) generator for reading the transmission rate matching buffer and receiving an output of the event counter and the amplifier T flag, (UTOPIA) of the ATM adapter provided with the transmission control signal generator (56) for generating the selection control signal and the strobe (STRB) signal for controlling the selecting means and the CRC control signal for controlling the transmission connection function, Transmission access device. 제1항에 있어서, 상기 이벤트 카운터(55)는 송신클럭을 모듈로 55로 카운터하는 것을 특징으로 하는 ATM 어답터의 유토피아(UTOPIA) 송신접속장치.The UTOPIA transmission access device of an ATM adapter according to claim 1, wherein the event counter (55) counts a transmission clock as a module (55). 제1항에 있어서, 상기 선택수단은 멀티플랙서(54)로 구현된 것을 특징으로 하는 ATM어답터의 유토피아(UTOPIA) 송신접속장치.3. The UTOPIA transmission access device of claim 1, wherein the selection means is implemented as a multiplexer (54). 제1항에 있어서, 상기 제어신호 발생부(56)는 이벤트 카운터(55)의 카운터 값이 0일 경우에는 엠프티 플래그(empty)를 조사하고, 조사결과 엠프티 플래그가 ‘하이’이면, 카운터값 1에서 동기신호(JK)명령을 송신하고, 카운터값 2에 시작신호 (TT)명령을 송신하며, 이어서 카운터값 3부터 55까지는 53바이트의 셀 데이타를 출력하게 하며, 엠프티 플래그가 ‘로우’이면 계속 동기신호(JK)명령을 송신하는 것을 특징으로 하는 ATM어답터의 유토피아(UTOPIA) 송신접속장치.2. The apparatus of claim 1, wherein the control signal generator (56) checks an empty flag when the counter value of the event counter (55) is 0, (JK) command is transmitted at a value 1 and a start signal (TT) command is transmitted at a counter value 2, and subsequently, cell data of 53 bytes from the counter value 3 to 55 are outputted. When the empty flag is set to ' (JK) command to the ATM adapter. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960007970A 1996-03-22 1996-03-22 Utopia sending connection apparatus of atm adaptor KR100212831B1 (en)

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KR100212831B1 KR100212831B1 (en) 1999-08-02

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100428667B1 (en) * 2001-07-18 2004-04-28 엘지전자 주식회사 A circuit of atm cell switching

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100433295B1 (en) * 1997-01-31 2005-05-24 삼성전자주식회사 Interface circuit between UTOPIA level 1,2 devices that can be implemented in PAL
KR19990075873A (en) * 1998-03-25 1999-10-15 김영환 Subscriber Asymmetric Digital Subscriber Line Modem of Asymmetric Digital Subscriber Line System

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100428667B1 (en) * 2001-07-18 2004-04-28 엘지전자 주식회사 A circuit of atm cell switching

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