KR970056383A

KR970056383A - ATM adaptive layer type 5 (AAL-5) recombination unit

Info

Publication number: KR970056383A
Application number: KR1019950053200A
Authority: KR
Inventors: 김현철; 이규호
Original assignee: 양승택; 한국전자통신연구원; 이준; 한국전기통신공사
Priority date: 1995-12-21
Filing date: 1995-12-21
Publication date: 1997-07-31

Abstract

본 발명은 ATM(Asynchronous Transfer Mode) 기술을 기반으로 한 광대역 종합 정보 통신망(ISDN)의 ATM 적응계층 타입 5(AAL-5 : ATM Adaptation Layer typeThe present invention relates to ATM Adaptation Layer type 5 (AAL-5) of a Broadband Integrated Services Network (ISDN) based on ATM (Asynchronous Transfer Mode) technology.

5) 수신측의 재결합 장치에 관한 것으로서, FIFO(10)로부터 FIFO_-EMPTY 신호가 수신되면 카운트 시작 신호를 출력하고, 카운트 값을 이용하여 FIFO 읽기 인에이블 (FIFO_-REN) 신호를 상기 FIFO(10)로 출력하는 FIFO 인터페이스 수단(21); 상기 FIFO 인터페이스 수단(21)의 카운트 시작 신호에 의해 계수하여 카운트 값을 출력하는 카운터 제어 수단(24); 헤더 값을 저장하는 헤더 테이블 수단(27); 상기 FIFO (10)로부터 셀 데이타(CELL_-DAT)를 입력받아 입력된 헤더 값과 상기 헤더 테이블 수단(27)에 저장된 헤더 값을 비교하여 출력하는 테이블 비교 수단(22); 상기 FIFO (10)로부터 셀 데이타를 입력받아 마지막 셀인지를 판별하여 출력하는 PTI 비교 수단(23); 상기 헤더 테이블 수단(27)을 제어하는 헤더 제어 수단(25); 시스템을 리셋 처리하는 리셋 처리 수단(26); 상기 PTI 비교 수단(23)의 제어에 의해 인터럽트 (DPRAM_-INT) 신호를 DPRAM(30)에 출력하는 CPU 인터페이스 수단(28); 및 상기 헤더 제어 수단(25)의 인덱스 값에 의해 상기 DPRAM(30)에 데이타를 저장하기 위한 주소(DPRAM_-ADD)와 DPRAM 읽기/쓰기(DPRAM_-RW) 신호, DPRAM 활성화(DPRAM_-CS) 신호를 출력하여 입력된 데이타를 상기 DPRAM(30)에 저장하는 DPRAM 인터페이스 수단(29)을 구비하여 실시간으로 ALL-5 재결합 기능을 수행하고, DPRAM 내의 가용 공간을 찾기 위한 별다른 시간과 로직이 필요하지 않기 때문에 고속으로 재결합 기능을 수행할 수 있는 효과가 있다.5) The apparatus for recombination on the receiving side, and when a FIFO _- EMPTY signal is received from the FIFO 10, outputs a count start signal, and outputs a FIFO read enable signal (FIFO _- REN) using the count value. FIFO interface means 21 for outputting; Counter control means (24) for counting by the count start signal of said FIFO interface means (21) and outputting a count value; Header table means 27 for storing a header value; Table comparison means (22) for receiving cell data (CELL _- DAT) from the FIFO (10) and comparing the input header value with the header value stored in the header table means (27); PTI comparison means (23) for receiving the cell data from the FIFO (10) to determine whether it is the last cell and to output it; Header control means (25) for controlling the header table means (27); Reset processing means (26) for resetting the system; CPU interface means (28) for outputting an interrupt (DPRAM _- INT) signal to DPRAM (30) under the control of said PTI comparing means (23); And an address (DPRAM _- ADD) for storing data in the DPRAM 30, a DPRAM read / write (DPRAM _- RW) signal, and a DPRAM activation (DPRAM _- CS) signal by an index value of the header control means 25. DPRAM interface unit 29 for outputting and storing the input data in the DPRAM 30 to perform the ALL-5 recombination function in real time, and does not require any time and logic for finding available space in the DPRAM. Therefore, the recombination function can be performed at high speed.

Description

ATM adaptive layer type 5 (AAL-5) recombination unit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 따른 에이티엠 적응계층 타입 5(AAL-5) 재결합 장치의 일실시예에 따른 블럭 구성도,1 is a block diagram according to an embodiment of an AEM-5 (AAL-5) recombination device according to the present invention;

제2도는 본 발명에 따른 에이티엠(ATM) 셀 수신 타이밍도,2 is a timing diagram of ATM cell reception according to the present invention;

제4도는 본 발명에 따른 테이블 비교부의 세부 회로도,4 is a detailed circuit diagram of a table comparison unit according to the present invention;

제6도는 본 발명에 따른 DPRAM 인터페이스부의 타이밍도.6 is a timing diagram of a DPRAM interface unit according to the present invention.

Claims

When a FIFO _- EMPTY signal is received from the FIFO 10 indicating that there is one or more data, a count start signal is output, and a FIFO read enable signal (FIFO _- REN) is output to the FIFO 10 using the count value. FIFO interface means 21; Counter control means (24) for counting by the count start signal of said FIFO interface means (21) and outputting a count value; Header table means 27 for storing a header value; Receives cell data (CELL _- DAT) from the FIFO 10 and compares the input header value with the header value stored in the header table means 27 and registers it in the header table means 27 if it is the first received value. Table comparison means (22) for outputting a control signal for outputting the control signal and for outputting an index value in the header table means (27) for the corresponding connection identifier (VPI / VCI) if the value is already registered; PTI comparison means (23) for receiving cell data from the FIFO (10) to determine whether the cell is the last cell and to output the cell; In response to the control signal of the table comparison means 22, the available memory of the header table means 27 is searched to register a header value or output an index value for the corresponding connection identifier, and the last value from the PTI comparison means 23 is obtained. Header control means (25) for setting a corresponding connection identifier (VPI / VCI) of the header table means (27) to '0' upon receiving a signal indicating that data is received; Reset processing means (26) for receiving a system reset signal to reset the system; CPU interface means (28) for receiving a signal indicating that the last data is received from the PIT comparing means (23) and outputting an interrupt (DPRAM _- INT) signal to the DPRAM (30); And an address (DPRAM _- ADD) for storing data in the DPRAM 30, a DPRAM read / write (DPRAM _- RW) signal, and a DPRAM activation (DPRAM _- CS) signal by an index value of the header control means 25. And an DPRAM interface means (29) for outputting and storing the input data in the DPRAM (30).

※ Note: The disclosure is based on the initial application.