KR960027776A

KR960027776A - Header Error Control Data Generation Circuit of Cell Header in Wideband Telecommunication Network

Info

Publication number: KR960027776A
Application number: KR1019940039964A
Authority: KR
Inventors: 이승열
Original assignee: 배순훈; 대우전자 주식회사
Priority date: 1994-12-30
Filing date: 1994-12-30
Publication date: 1996-07-22

Abstract

본 발명은 셀 헤더부의 헤더오류제어 데이타 생성회로에 관한 것으로서, CRC 계산을 한 뒤 그 값을 다시 ATM 계층용 FIFO 메모리에 저장하지 않고, 데이타를 전송하는 것과 동시에 CRC 계산을 함으로써 시스템의 전송속도를 향상시킬 수 있고, 또한 ATM 계층용 FIFO 메모리의 용량을 줄일 수 있다.The present invention relates to a header error control data generating circuit of a cell header unit. The present invention relates to a system for transmitting a data by simultaneously performing CRC calculation after performing CRC calculation and storing the data in a FIFO memory for ATM layer. It can improve and also reduce the capacity of FIFO memory for ATM layer.

Description

Header Error Control Data Generation Circuit of Cell Header in Wideband Telecommunication Network

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 적용되는 데이타의 계층을 설명하기 위한 블럭도, 제3도는 광대역종합통신망에 있어서 본 발명에 의한 셀 헤더부의 헤더오류제어 데이타 생성회로를 나타낸 회로도.1 is a block diagram for explaining a hierarchy of data applied to the present invention, and FIG. 3 is a circuit diagram showing a header error control data generation circuit of a cell header unit according to the present invention in a broadband integrated communication network.

Claims

A first register for reading and storing 4 bytes of header data from the FIFO memory for ATM layer; A second register for generating HEC data by calculating a CRC value from the 4-byte header data; The 4-byte header data output from the first register, the 1-byte HEC data output from the second register, and the 48-byte data read from the ATM layer FIFO memory are multiplexed and transmitted according to a selection control signal. And a multiplexer for outputting to a register, wherein the header error control data generation circuit is included in the cell header.

2. The multiplexer of claim 1, wherein the multiplexer reads four bytes of header data output from the first register, writes the data to the transfer register, and writes one byte of HEC data output from the second register to the transfer register. And repeating the step of sequentially reading the 48-byte data from the ATM layer FIFO memory and sequentially writing the data to the transfer register.

2. The header error control data generation circuit of claim 1, wherein the selection control signal uses a count value output from a 52 event counter.

※ Note: The disclosure is based on the initial application.