KR0126850B1 - Apparatus eliminating error packet for fixed-length parcket communications system - Google Patents

Abstract

A pause packet removing apparatus for a fixed length packet communication includes: input register(10) for receiving an external input clock signal(ICLK) and a packet data [ID(8:0) of 8-bit width and arranging it; a packet input controller(20) for determining if the output packet from the input register(10) is stored in FIFO memory(30) or not, and generating a control signal; a packet output controller(40) for generating a control signal to output a packet stored in the FIFO memory(30) according to a control of the packet input controller(40); and an output register(50) for arranging an output data of the FIFO memory(30) according to a control of the packet output controller(40). The pause packet removing apparatus prevents a system hindrance caused by an incomplete packet, and removes a pause packet although a packet longer than a fixed length is received or a short packet is received.

Description

Idle packet removal device for fixed length packet communication

1 is a block diagram of a tissue packet removing device according to the present invention.

2 is a state transition diagram of the packet input control unit of FIG.

3 is a state transition diagram of the packet output control unit of FIG.

* Explanation of symbols for main parts of the drawings

10,50: register 20: packet input control unit

30: FIFO memory 40: packet output control unit

The present invention relates to an idle packet removal device for fixed length packet communication, and more particularly, to an idle packet removal device for removing an incomplete packet (pause packet) generated due to an unexpected cause in fixed length packet communication. .

FIFO (First-In-First-Out) memory is used for buffering data between two different speed points such as graphic, LAN, and IPC (temporary buffering) and temporary buffering for processing time. It is used. In particular, in fixed-length packet communication such as asynchronous transmission mode (ATM) LAN as well as B-ISDN in the future, a large number of FIFO memories of an integer multiple of the fixed packet length are used to temporarily store input packets. do.

However, if a packet that does not form a fixed-length packet is inserted in the middle of the FIFO memory, it causes a fatal failure in subsequent communication services. Therefore, these idle packets should be removed to prevent the system from affecting.

Accordingly, the present invention has been made to solve the above problems, in fixed-length packet communication using a FIFO memory having an input and output function synchronized to the clock, to protect the system from misinserted unconfigured idle packets It is an object of the present invention to provide an idle packet removing device for fixed length packet communication for removing idle packets.

In order to achieve the above object, the present invention provides an 8-bit wide packet data [ID (8) including one bit ID8 which is synchronized with the input clock signal ICLK from the outside and indicates a byte of the packet. 0)] input register for receiving and sorting; A FIFO packet is output from the input register 10 by receiving an FF flag indicating the full state of the FIFO memory, a bit ID8 indicating the start byte of the packet, and a valid signal ICEN indicating the validity of the current packet. A packet input control unit for determining whether to store in a memory and outputting a write enable signal WEN, a signal WD8 indicating the start of a packet, and a stop signal ISTOP for stopping input when the FIFO memory is in a full state; A signal indicating that output is available (OSTOP), an EF flag indicating that there is a packet stored in the FIFO memory, and a bit (RD8) indicating the start byte of the packet is stored in the FIFO memory. A packet output control unit for outputting a read enable signal REN, a read clock RCLK, an output enable signal OE, and a valid signal OCEN indicating validity of an output packet for outputting a packet #; And an output register for arranging data output from the FIFO memory under the control of the packet output controller.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating an idle packet removing apparatus according to the present invention. The input register 10 is an 8-bit width including one bit ID8 indicating a start byte of a packet synchronized with the input clock signal ICLK. The input packet data [ID (8: 0)] is inputted and sorted, and the timing used to determine whether the packet input control unit 20 stores the packet data [ID (8: 0)] in the FIFO memory 30 is determined. To match.

The packet input control unit 20 has an FF flag indicating the full state of the FIFO memory 30, a bit ID8 indicating the start byte of the packet, and a valid signal ICEN indicating the validity (zero when valid) of the current packet. Stops input when the write enable signal WEN, the signal WD8 indicating the start of the packet, and the FIFO memory 30 are in a full state. Output a stop signal (ISTOP) for

On the other hand, the packet output control unit 40 reads the enable signal REN and the read clock RCLK when there is a packet stored in the FIFO memory 30 when the output is enabled (OSTOP = 0). The output enable signal OE is input to the FIFO memory 30 to read and transmit the packet, and also output a signal OCEN indicating its validity.

The output register 50 sorts the data output from the FIFO memory 30 under the control of the packet output control unit 40.

In addition, the packet input control unit 20 and the packet output control unit 40 have a flag indicating the state of the FIFO memory 30, that is, a flag FF indicating the full state of the FIFO memory 30 and the FIFO memory 30. A flag EF indicating that there is a stored packet may be used to control the flow of packets between components.

2 is a state transition diagram of the packet input control unit 20.

In the idle state SI1, the FIFO memory 30 is full (FF = 1) or there is no packet start signal (ID8 = 0), or there is a packet start signal (ID8 = 1) but the packet is valid. If not (ICEN = 1), the signal is kept in the IDLE state (SI1) and outputs a signal (WD8 = 0) and a write protection signal (WEN = 1) indicating that the packet is not at the beginning, and stores the packet in the FIFO memory 30. Do not do it.

However, if the FIFO memory 30 is not full (FF = 0) and the start of a valid packet (INE = 0) (ID8 = 1), the FIFO memory 30 transitions to the byte initialization state S12 to initialize the write byte count (WBNT = 0), a signal indicating the start of a packet (WD8 = 1) and a write enable signal (WEN = 0) are output to store data in one byte unit in the FIFO memory 30, and the byte count increment state ( Transition to SI3) increases the byte count (WBNT) by one.

On the other hand, in the byte count increment state SI3, the signal WD8 = 0 and the write enable signal WEN = 0 are continuously output to indicate that the packet is not at the beginning, so that bytes of the contiguous fixed packet length (N) are stored. It stores in the FIFO memory 30.

If the write byte count (WBNT) does not increase by the fixed packet length (N), the above operation is repeated, and when the FIFO memory 30 is in the full state when the received byte count (N) is received by the fixed packet length (N) (WBNT = N-1). The write protection signal WEN = 1 and the signal WD8 = 0 indicating that the packet is not started are outputted so that the packet is not stored in the FIFO memory 30, and the state transitions to the IDLE state SI1.

On the other hand, when the fixed packet length (N) is accepted (WBNT = N-1), if the FIFO memory 30 is not full (FF = 0) and the start of a valid packet (ICEN = 0) (ID8 = 1), the byte Transition to the initialization state (SI2) initializes the write byte count (WBNT = 0), outputs the signal indicating the start of the packet (WD8 = 1) and the write enable signal (WEN = 0) to output the packet to the FIFO memory (30). ).

By repeatedly performing the above operation, the packet input control unit 20 may prevent a failure of the system due to an unfinished packet that is unexpectedly input. In addition, even if a packet longer than a fixed length is received due to a cause such as a glitch of the reception input clock, the packet input control unit 20 receives only a fixed length packet and discards the rest, and a packet shorter than the fixed length (N). When received, the missing part is filled with 0 and stored, thereby preventing cell loss caused by the idle packet.

3 is a state transition diagram of the packet output control unit 40.

When the FIFO memory 30 is empty (EF = 1) or the output stop signal OSTOP = 1 is applied in the idle state ID1, the prevention signal REN = 1 and the output prevention signal ( Output OE = 1) to remain in IDLE state.

However, when the output is enabled (OSTOP = 0), if there is a packet stored in the FIFO memory 30 (EF = 0), the state is transferred to the byte initialization state (SO2) to initialize the read byte count (RBNT = 0). A signal for reading and transmitting a packet by inputting a read enable signal (REN = 0), a read clock RCLK and an output enable signal (OE = 0) to the FIFO memory 30, and also indicating a valid signal thereof ( OCEN = 0) is outputted and the state transitions to the byte count increment state SO3.

After increasing the byte count (RBNT) by 1 in the byte count increment state (SO3), if the most significant bit of the read byte indicates the start of the packet (RD8 = 1), it continues from the FIFO memory 30 to the length of one packet. The read enable signal REN = 0, the read clock RCLK, and the output enable signal OE = 0 are outputted to read and transmit, and the byte count increment state SO4 is shifted.

On the other hand, if it is not the start of the packet in the byte count increment state SO3 (RD8 = 0), the already read byte is discarded and the byte count is initialized (SO2) to initialize the byte count (RBNT = 0), and then again. Repeat the above procedure to restore cell motivation.

When the packet is read and transmitted by the fixed packet length N in the byte count increment state SO4 (RBNT = N-1), the packet to be transmitted remains in the FIFO memory 30 (EF = 0). If possible (OE = 0), the procedure is repeated by transitioning to the byte initialization state SO2. Accordingly, even if an error occurs in the input, it can find the cell synchronization at the output and output the fixed length packet according to the synchronization.

As described above, the present invention can prevent a system failure due to an unfinished packet that is unexpectedly input, and even if a packet longer than a fixed length or a short packet is received due to a cause such as a glitch of a received input clock. By removing such a pause packet, it is possible to prevent loss of cell synchronization.

Claims (1)

Input register 10 for receiving and sorting 8-bit wide packet data [ID (8: 0)] including an externally input clock signal ICLK and one bit ID8 indicating the start byte of the packet. The input register 10 receives the FF flag indicating the full state of the FIFO memory 30, a bit ID8 indicating the start byte of the packet from the outside, and a valid signal ICEN indicating the validity of the current packet. It is determined whether to store the packet output from the FIFO memory FIFO memory 30, and provides the write enable signal WEN and the signal WD8 indicating the start of the packet to the FIFO memory 30, and the FIFO memory 30 Packet input control unit 20 for outputting a stop signal (ISTOP) to stop input when the state is full; EF flag indicating that there is a packet stored in the FIFO memory 30 and the most significant bit of the read byte. Start of packet A bit RD8 indicating a signal and a signal REN indicating that an output is possible from the outside, a read clock RCLK, and an output enable signal OE are provided to the FIFO memory 30, and the output packet is valid. A packet output control unit 40 for outputting a valid signal OCEN indicating to the outside; And an output register (50) for arranging data output from the FIFO memory (30) under the control of the packet output control unit (40).