KR970067616A - 자기 정렬 초박막층을 사용한 cvd 알루미늄의 선택적 블랭킷 증착 및 반사율 개선 방법 - Google Patents

자기 정렬 초박막층을 사용한 cvd 알루미늄의 선택적 블랭킷 증착 및 반사율 개선 방법 Download PDF

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KR970067616A
KR970067616A KR1019970007160A KR19970007160A KR970067616A KR 970067616 A KR970067616 A KR 970067616A KR 1019970007160 A KR1019970007160 A KR 1019970007160A KR 19970007160 A KR19970007160 A KR 19970007160A KR 970067616 A KR970067616 A KR 970067616A
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타이 구오 테드
첸 리앙-유흐
첸 푸센
크라이그 모슬리 로데릭
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조셉 제이. 스위니
어플라이드 머터어리얼스, 인코포레이티드
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    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating

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Abstract

본 발명은 일반적으로 박막 특성과 증착 커버리지를 개선하기위해 도전 박막 층의 형성 이전에 자기정렬 박막 층을 제공하는 개선된 장치 및 방법에 관한 것이다. 본 발명의 한 특징에서, 유전체 층은 도전 또는 반도전층 상에 형성되고 개구부 바닥에 하부 도전 반도전 층을 노출하기 위한 개구부를 형성하기 위해 에칭된다. 다음에 초박막 핵 형성층은 기상 증착 또는 화학 기상 증착에 의해 유전체 층의 필드에 증착된다. 다음 CVD 금속층은 개구부의 바닥에 선택적 증착을 얻기 위해 가판상에 증착되고, 바람직하게 상기 필드에 높은 방향성 블랭킷 층을 형성한다. 본 발명의 다른 특징에서, 자기정렬 박막층은 도전층이 증착되기 이전에 장벽층 상에 형성된다. 자기 정렬층은 얻어진 박막의 결정구조를 개선시킴으로써 박막의 반사율을 증진시키고＜111＞ 결정방향을 제공함으로써 개선된 전자 이동을 제공한다. 상기 방법은 바람직하게 기판이 진공 환경에 유입될 때 처리가 층 사이의 산화물 형성없이 발생하도록 PVD와 CVD 처리 챔버 둘 다를 포함하는 통합된 처리 시스템에서 수행된다.

Description

자기 정렬 초박막층을 사용한 CVD 알루미늄의 선택적 블랭킷 증착 및 반사율 개선 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 하나의 특징에 따른 여러 가지 증착층을 도시하는 기판의 단면도.

Claims (18)

  1. 제품 상의 높은 방향성 막 형성 방법에 있어서, a) 상기 제품 상에 적어도 하나의 증착 재료의 얇은 엡실론층을 증착하는 단계; 및 b) 상기 얇은 엡실론층 상에 도전층을 순차적으로 증착하는 단계를 포함하는 것을 특징으로 하는 방법.
  2. 제1항에 있어서, 상기 엡실론층은 Ti, TiN, Al, Nb, Ta, 알루미늄 실리케이트, 실리카, 고급 알루미나 및 이들의 혼합물로 구성되는 그룹으로부터 선택된 재료로부터 형성되는 것을 특징으로 하는 방법.
  3. 제2항에 있어서, 상기 얇은 엡실론층 상에 제2얇은 엡실론층을 증착하는 단계를 더 포함하는데, 상기 제2엡실론층은 Ti, TiN, Al, Nb, Ta, 알루미늄 실리케이트, 실리카, 고급 알루미나로 구성되는 그룹으로부터 선택되는 것을 특징으로 하는 방법.
  4. 제1항에 있어서, 상기 도전 재료는 알루미늄인 것을 특징으로 하는 방법.
  5. 제4항에 있어서, 상기 도전층은 CVD에 의해 증착되는 것을 특징으로 하는 방법.
  6. 제1항에 있어서, 상기 얇은 엡실론층은 Ti, TiN 및 Al로 구성된 그룹으로부터 선택되는 다수의 재료를 포함하는 것을 특징으로 하는 방법.
  7. 제5항에 있어서, 상기 핵 형성층은 티타늄, 질화 티타늄, 알루미늄, Nb, 알루미늄 실리케이트, 실리카, 고급 알루미나, Si, Cu, Ta 및 이들의 혼합물로 구성되는 그룹으로부터 선택되는 것을 특징으로 하는 방법.
  8. 제1항에 있어서, 상기 얇은 엡실론층은 장벽층 상에 증착되는 것을 특징으로 하는 방법.
  9. 제8항에 있어서, 상기 도전 재료는 물리적 기상 증착에 의해 증착되는 것을 특징으로 하는 방법.
  10. 제9항에 있어서, 알루미늄의 상기 물리적 기상 증착은 약400℃이상의 온도에서 발생하는 것을 특징으로 하는 방법.
  11. 제10항에 있어서, 상기 도전 재료는 알루미늄이고, 상기 물리적 기상 증착된 알루미늄은 도판트를 포함하며, 약250℃ 내지 약350℃사이의 온도에서 어닐링하는 단계를 더 포함하는 것을 특징으로 하는 방법.
  12. 제1항에 있어서, 상기 방법은 통합된 처리 시스템에서 수행되는 것을 특징으로 하는 방법.
  13. 반도체 기판 처리 장치에 있어서, a) 적어도 하나의 PVD챔버와 적어도 하나의 CVD챔버를 가지는 계획된 처리챔버; b) 선택된 챔버의 내부와 외부로 상기 처리 시스템을 통해 기판을 이동하기 위한 전송 부재; 및 c) 상기 시스템을 통한 기판의 이동을 제어하고 상기 기판 상에서 형성되는 과정을 제어하기 위한 마이크로프로세서 제어기를 포함하는 것을 특징으로 하는 반도체 기판 처리 장치.
  14. 제13항에 있어서, 기판이 PVD챔버에 위치되고, Ti, TiN 및 Al로부터 선택된 적어도 하나의 재료의 박막층이 상기 기판 상에 증착되며, 도전층이 높은 방형성 도전 박막층을 형성하기 위해 상기 적어도 하나의 재료의 박막층 상에 증착되는 것을 특징으로 하는 반도체 기판 처리 장치.
  15. 제14항에 있어서, 상기 순차적 도전층은 PVD에 의해 증착되는 것을 특징으로 하는 반도체 기판 처리 장치.
  16. 제14항에 있어서, 상기 순차적 도전층은 CVD에 의해 증착되는 것을 특징으로 하는 반도체 기판 처리 장치.
  17. 제14항에 있어서, 상기 순차적 도전층은 알루미늄인 것을 특징으로 하는 반도체 기판 처리 장치.
  18. 박막층의 반사율 개선 방법에 있어서, a) 기판의 표면 상에 균일한 박막층을 제공하는 단계; b) 상기 균일한 박막층 상에 소량의 스퍼터링된 자기 정렬 엡실론 재료를 제공하는 단계; 및 c) 상기 엡실론 재료 상에 도체를 증착하는 단계를 포함하는 것을 특징으로 하는 박막층의 반사율 개선 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019970007160A 1996-03-05 1997-03-05 자기 정렬 초박막층을 사용한 cvd 알루미늄의 선택적 블랭킷 증착 및 반사율 개선 방법 KR970067616A (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US08/611,108 1996-03-05
US08/611,108 US6066358A (en) 1995-11-21 1996-03-05 Blanket-selective chemical vapor deposition using an ultra-thin nucleation layer
US08/622,941 US6120844A (en) 1995-11-21 1996-03-27 Deposition film orientation and reflectivity improvement using a self-aligning ultra-thin layer
US08/622,941 1996-03-27

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US6120844A (en) 2000-09-19

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