KR970067616A - 자기 정렬 초박막층을 사용한 cvd 알루미늄의 선택적 블랭킷 증착 및 반사율 개선 방법 - Google Patents
자기 정렬 초박막층을 사용한 cvd 알루미늄의 선택적 블랭킷 증착 및 반사율 개선 방법 Download PDFInfo
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- KR970067616A KR970067616A KR1019970007160A KR19970007160A KR970067616A KR 970067616 A KR970067616 A KR 970067616A KR 1019970007160 A KR1019970007160 A KR 1019970007160A KR 19970007160 A KR19970007160 A KR 19970007160A KR 970067616 A KR970067616 A KR 970067616A
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- 230000008021 deposition Effects 0.000 title claims abstract description 5
- 229910052782 aluminium Inorganic materials 0.000 title claims 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 title claims 7
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract 20
- 239000010409 thin film Substances 0.000 claims abstract 12
- 238000000151 deposition Methods 0.000 claims abstract 8
- 238000005240 physical vapour deposition Methods 0.000 claims abstract 6
- 230000004888 barrier function Effects 0.000 claims abstract 2
- 230000006911 nucleation Effects 0.000 claims abstract 2
- 238000010899 nucleation Methods 0.000 claims abstract 2
- 238000002310 reflectometry Methods 0.000 claims abstract 2
- 239000000463 material Substances 0.000 claims 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 6
- 239000010936 titanium Substances 0.000 claims 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims 4
- 239000004020 conductor Substances 0.000 claims 4
- 229910052718 tin Inorganic materials 0.000 claims 4
- YKTSYUJCYHOUJP-UHFFFAOYSA-N [O--].[Al+3].[Al+3].[O-][Si]([O-])([O-])[O-] Chemical compound [O--].[Al+3].[Al+3].[O-][Si]([O-])([O-])[O-] YKTSYUJCYHOUJP-UHFFFAOYSA-N 0.000 claims 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims 3
- 239000000377 silicon dioxide Substances 0.000 claims 3
- 229910052715 tantalum Inorganic materials 0.000 claims 3
- 229910052719 titanium Inorganic materials 0.000 claims 3
- 239000000203 mixture Substances 0.000 claims 2
- 229910052758 niobium Inorganic materials 0.000 claims 2
- 239000004065 semiconductor Substances 0.000 claims 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical group [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims 1
- 238000000137 annealing Methods 0.000 claims 1
- 239000002019 doping agent Substances 0.000 claims 1
- 239000010408 film Substances 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 abstract 2
- 239000013078 crystal Substances 0.000 abstract 2
- 238000005229 chemical vapour deposition Methods 0.000 abstract 1
- 239000002184 metal Substances 0.000 abstract 1
- 230000027756 respiratory electron transport chain Effects 0.000 abstract 1
- 238000007740 vapor deposition Methods 0.000 abstract 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76876—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for deposition from the gas phase, e.g. CVD
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
- C23C14/56—Apparatus specially adapted for continuous coating; Arrangements for maintaining the vacuum, e.g. vacuum locks
- C23C14/568—Transferring the substrates through a series of coating stations
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/54—Apparatus specially adapted for continuous coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32051—Deposition of metallic or metal-silicide layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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Abstract
본 발명은 일반적으로 박막 특성과 증착 커버리지를 개선하기위해 도전 박막 층의 형성 이전에 자기정렬 박막 층을 제공하는 개선된 장치 및 방법에 관한 것이다. 본 발명의 한 특징에서, 유전체 층은 도전 또는 반도전층 상에 형성되고 개구부 바닥에 하부 도전 반도전 층을 노출하기 위한 개구부를 형성하기 위해 에칭된다. 다음에 초박막 핵 형성층은 기상 증착 또는 화학 기상 증착에 의해 유전체 층의 필드에 증착된다. 다음 CVD 금속층은 개구부의 바닥에 선택적 증착을 얻기 위해 가판상에 증착되고, 바람직하게 상기 필드에 높은 방향성 블랭킷 층을 형성한다. 본 발명의 다른 특징에서, 자기정렬 박막층은 도전층이 증착되기 이전에 장벽층 상에 형성된다. 자기 정렬층은 얻어진 박막의 결정구조를 개선시킴으로써 박막의 반사율을 증진시키고<111> 결정방향을 제공함으로써 개선된 전자 이동을 제공한다. 상기 방법은 바람직하게 기판이 진공 환경에 유입될 때 처리가 층 사이의 산화물 형성없이 발생하도록 PVD와 CVD 처리 챔버 둘 다를 포함하는 통합된 처리 시스템에서 수행된다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 하나의 특징에 따른 여러 가지 증착층을 도시하는 기판의 단면도.
Claims (18)
- 제품 상의 높은 방향성 막 형성 방법에 있어서, a) 상기 제품 상에 적어도 하나의 증착 재료의 얇은 엡실론층을 증착하는 단계; 및 b) 상기 얇은 엡실론층 상에 도전층을 순차적으로 증착하는 단계를 포함하는 것을 특징으로 하는 방법.
- 제1항에 있어서, 상기 엡실론층은 Ti, TiN, Al, Nb, Ta, 알루미늄 실리케이트, 실리카, 고급 알루미나 및 이들의 혼합물로 구성되는 그룹으로부터 선택된 재료로부터 형성되는 것을 특징으로 하는 방법.
- 제2항에 있어서, 상기 얇은 엡실론층 상에 제2얇은 엡실론층을 증착하는 단계를 더 포함하는데, 상기 제2엡실론층은 Ti, TiN, Al, Nb, Ta, 알루미늄 실리케이트, 실리카, 고급 알루미나로 구성되는 그룹으로부터 선택되는 것을 특징으로 하는 방법.
- 제1항에 있어서, 상기 도전 재료는 알루미늄인 것을 특징으로 하는 방법.
- 제4항에 있어서, 상기 도전층은 CVD에 의해 증착되는 것을 특징으로 하는 방법.
- 제1항에 있어서, 상기 얇은 엡실론층은 Ti, TiN 및 Al로 구성된 그룹으로부터 선택되는 다수의 재료를 포함하는 것을 특징으로 하는 방법.
- 제5항에 있어서, 상기 핵 형성층은 티타늄, 질화 티타늄, 알루미늄, Nb, 알루미늄 실리케이트, 실리카, 고급 알루미나, Si, Cu, Ta 및 이들의 혼합물로 구성되는 그룹으로부터 선택되는 것을 특징으로 하는 방법.
- 제1항에 있어서, 상기 얇은 엡실론층은 장벽층 상에 증착되는 것을 특징으로 하는 방법.
- 제8항에 있어서, 상기 도전 재료는 물리적 기상 증착에 의해 증착되는 것을 특징으로 하는 방법.
- 제9항에 있어서, 알루미늄의 상기 물리적 기상 증착은 약400℃이상의 온도에서 발생하는 것을 특징으로 하는 방법.
- 제10항에 있어서, 상기 도전 재료는 알루미늄이고, 상기 물리적 기상 증착된 알루미늄은 도판트를 포함하며, 약250℃ 내지 약350℃사이의 온도에서 어닐링하는 단계를 더 포함하는 것을 특징으로 하는 방법.
- 제1항에 있어서, 상기 방법은 통합된 처리 시스템에서 수행되는 것을 특징으로 하는 방법.
- 반도체 기판 처리 장치에 있어서, a) 적어도 하나의 PVD챔버와 적어도 하나의 CVD챔버를 가지는 계획된 처리챔버; b) 선택된 챔버의 내부와 외부로 상기 처리 시스템을 통해 기판을 이동하기 위한 전송 부재; 및 c) 상기 시스템을 통한 기판의 이동을 제어하고 상기 기판 상에서 형성되는 과정을 제어하기 위한 마이크로프로세서 제어기를 포함하는 것을 특징으로 하는 반도체 기판 처리 장치.
- 제13항에 있어서, 기판이 PVD챔버에 위치되고, Ti, TiN 및 Al로부터 선택된 적어도 하나의 재료의 박막층이 상기 기판 상에 증착되며, 도전층이 높은 방형성 도전 박막층을 형성하기 위해 상기 적어도 하나의 재료의 박막층 상에 증착되는 것을 특징으로 하는 반도체 기판 처리 장치.
- 제14항에 있어서, 상기 순차적 도전층은 PVD에 의해 증착되는 것을 특징으로 하는 반도체 기판 처리 장치.
- 제14항에 있어서, 상기 순차적 도전층은 CVD에 의해 증착되는 것을 특징으로 하는 반도체 기판 처리 장치.
- 제14항에 있어서, 상기 순차적 도전층은 알루미늄인 것을 특징으로 하는 반도체 기판 처리 장치.
- 박막층의 반사율 개선 방법에 있어서, a) 기판의 표면 상에 균일한 박막층을 제공하는 단계; b) 상기 균일한 박막층 상에 소량의 스퍼터링된 자기 정렬 엡실론 재료를 제공하는 단계; 및 c) 상기 엡실론 재료 상에 도체를 증착하는 단계를 포함하는 것을 특징으로 하는 박막층의 반사율 개선 방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/611,108 | 1996-03-05 | ||
US08/611,108 US6066358A (en) | 1995-11-21 | 1996-03-05 | Blanket-selective chemical vapor deposition using an ultra-thin nucleation layer |
US08/622,941 US6120844A (en) | 1995-11-21 | 1996-03-27 | Deposition film orientation and reflectivity improvement using a self-aligning ultra-thin layer |
US08/622,941 | 1996-03-27 |
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KR970067616A true KR970067616A (ko) | 1997-10-13 |
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KR1019970007160A KR970067616A (ko) | 1996-03-05 | 1997-03-05 | 자기 정렬 초박막층을 사용한 cvd 알루미늄의 선택적 블랭킷 증착 및 반사율 개선 방법 |
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Country | Link |
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US (1) | US6120844A (ko) |
EP (1) | EP0794568A3 (ko) |
JP (1) | JPH1041247A (ko) |
KR (1) | KR970067616A (ko) |
Families Citing this family (32)
Publication number | Priority date | Publication date | Assignee | Title |
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US6077781A (en) * | 1995-11-21 | 2000-06-20 | Applied Materials, Inc. | Single step process for blanket-selective CVD aluminum deposition |
US6537905B1 (en) * | 1996-12-30 | 2003-03-25 | Applied Materials, Inc. | Fully planarized dual damascene metallization using copper line interconnect and selective CVD aluminum plug |
US6139905A (en) * | 1997-04-11 | 2000-10-31 | Applied Materials, Inc. | Integrated CVD/PVD Al planarization using ultra-thin nucleation layers |
US6143362A (en) | 1998-02-25 | 2000-11-07 | Micron Technology, Inc. | Chemical vapor deposition of titanium |
US6284316B1 (en) | 1998-02-25 | 2001-09-04 | Micron Technology, Inc. | Chemical vapor deposition of titanium |
US6057236A (en) * | 1998-06-26 | 2000-05-02 | International Business Machines Corporation | CVD/PVD method of filling structures using discontinuous CVD AL liner |
US6351036B1 (en) * | 1998-08-20 | 2002-02-26 | The United States Of America As Represented By The Secretary Of The Navy | Electronic devices with a barrier film and process for making same |
US6365059B1 (en) | 2000-04-28 | 2002-04-02 | Alexander Pechenik | Method for making a nano-stamp and for forming, with the stamp, nano-size elements on a substrate |
US20040195202A1 (en) * | 2000-04-28 | 2004-10-07 | Alexander Pechenik | Method for making a nano-stamp and for forming, with the stamp, nano-size elements on a substrate |
US6465887B1 (en) * | 2000-05-03 | 2002-10-15 | The United States Of America As Represented By The Secretary Of The Navy | Electronic devices with diffusion barrier and process for making same |
US6458416B1 (en) | 2000-07-19 | 2002-10-01 | Micron Technology, Inc. | Deposition methods |
US7192888B1 (en) | 2000-08-21 | 2007-03-20 | Micron Technology, Inc. | Low selectivity deposition methods |
US7368014B2 (en) | 2001-08-09 | 2008-05-06 | Micron Technology, Inc. | Variable temperature deposition methods |
US6835616B1 (en) | 2002-01-29 | 2004-12-28 | Cypress Semiconductor Corporation | Method of forming a floating metal structure in an integrated circuit |
US7026235B1 (en) | 2002-02-07 | 2006-04-11 | Cypress Semiconductor Corporation | Dual-damascene process and associated floating metal structures |
US7192867B1 (en) | 2002-06-26 | 2007-03-20 | Cypress Semiconductor Corporation | Protection of low-k dielectric in a passivation level |
US6660661B1 (en) | 2002-06-26 | 2003-12-09 | Cypress Semiconductor Corporation | Integrated circuit with improved RC delay |
US6977217B1 (en) | 2002-12-03 | 2005-12-20 | Cypress Semiconductor Corporation | Aluminum-filled via structure with barrier layer |
US6936496B2 (en) | 2002-12-20 | 2005-08-30 | Hewlett-Packard Development Company, L.P. | Nanowire filament |
US20040126482A1 (en) * | 2002-12-31 | 2004-07-01 | Chih-I Wu | Method and structure for selective surface passivation |
US7223611B2 (en) * | 2003-10-07 | 2007-05-29 | Hewlett-Packard Development Company, L.P. | Fabrication of nanowires |
US7132298B2 (en) * | 2003-10-07 | 2006-11-07 | Hewlett-Packard Development Company, L.P. | Fabrication of nano-object array |
US7407738B2 (en) * | 2004-04-02 | 2008-08-05 | Pavel Kornilovich | Fabrication and use of superlattice |
US20050241959A1 (en) * | 2004-04-30 | 2005-11-03 | Kenneth Ward | Chemical-sensing devices |
US7247531B2 (en) * | 2004-04-30 | 2007-07-24 | Hewlett-Packard Development Company, L.P. | Field-effect-transistor multiplexing/demultiplexing architectures and methods of forming the same |
US7727820B2 (en) * | 2004-04-30 | 2010-06-01 | Hewlett-Packard Development Company, L.P. | Misalignment-tolerant methods for fabricating multiplexing/demultiplexing architectures |
US7683435B2 (en) * | 2004-04-30 | 2010-03-23 | Hewlett-Packard Development Company, L.P. | Misalignment-tolerant multiplexing/demultiplexing architectures |
US7375012B2 (en) * | 2005-02-28 | 2008-05-20 | Pavel Kornilovich | Method of forming multilayer film |
DE102006057386A1 (de) * | 2006-12-04 | 2008-06-05 | Uhde Gmbh | Verfahren zum Beschichten von Substraten |
JP2008141050A (ja) * | 2006-12-04 | 2008-06-19 | Ulvac Japan Ltd | 半導体装置の製造方法及び半導体装置の製造装置 |
US9806041B1 (en) * | 2016-04-22 | 2017-10-31 | Infineon Technologies Ag | Method for processing an electronic component and an electronic component |
US11421318B2 (en) | 2018-05-04 | 2022-08-23 | Applied Materials, Inc. | Methods and apparatus for high reflectivity aluminum layers |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4960732A (en) * | 1987-02-19 | 1990-10-02 | Advanced Micro Devices, Inc. | Contact plug and interconnect employing a barrier lining and a backfilled conductor material |
US4897287A (en) * | 1988-10-06 | 1990-01-30 | The Boc Group, Inc. | Metallization process for an integrated circuit |
US4923717A (en) * | 1989-03-17 | 1990-05-08 | Regents Of The University Of Minnesota | Process for the chemical vapor deposition of aluminum |
US5232872A (en) * | 1989-05-09 | 1993-08-03 | Fujitsu Limited | Method for manufacturing semiconductor device |
US5240505A (en) * | 1989-08-03 | 1993-08-31 | Mitsubishi Denki Kabushiki Kaisha | Method of an apparatus for forming thin film for semiconductor device |
US5310410A (en) * | 1990-04-06 | 1994-05-10 | Sputtered Films, Inc. | Method for processing semi-conductor wafers in a multiple vacuum and non-vacuum chamber apparatus |
US5345108A (en) * | 1991-02-26 | 1994-09-06 | Nec Corporation | Semiconductor device having multi-layer electrode wiring |
US5250467A (en) * | 1991-03-29 | 1993-10-05 | Applied Materials, Inc. | Method for forming low resistance and low defect density tungsten contacts to silicon semiconductor wafer |
EP0535864B1 (en) * | 1991-09-30 | 1998-07-29 | AT&T Corp. | Fabrication of a conductive region in electronic devices |
US5371042A (en) * | 1992-06-16 | 1994-12-06 | Applied Materials, Inc. | Method of filling contacts in semiconductor devices |
KR970001883B1 (ko) * | 1992-12-30 | 1997-02-18 | 삼성전자 주식회사 | 반도체장치 및 그 제조방법 |
JPH0722339A (ja) * | 1993-07-05 | 1995-01-24 | Toshiba Corp | 薄膜形成方法 |
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1997
- 1997-03-04 EP EP97103489A patent/EP0794568A3/en not_active Withdrawn
- 1997-03-05 JP JP9091301A patent/JPH1041247A/ja active Pending
- 1997-03-05 KR KR1019970007160A patent/KR970067616A/ko not_active Application Discontinuation
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EP0794568A3 (en) | 1998-09-30 |
EP0794568A2 (en) | 1997-09-10 |
JPH1041247A (ja) | 1998-02-13 |
US6120844A (en) | 2000-09-19 |
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