KR970054538A - T-type gate formation method - Google Patents

T-type gate formation method Download PDF

Info

Publication number
KR970054538A
KR970054538A KR1019950052637A KR19950052637A KR970054538A KR 970054538 A KR970054538 A KR 970054538A KR 1019950052637 A KR1019950052637 A KR 1019950052637A KR 19950052637 A KR19950052637 A KR 19950052637A KR 970054538 A KR970054538 A KR 970054538A
Authority
KR
South Korea
Prior art keywords
type gate
photosensitive film
semiconductor substrate
forming
ultraviolet light
Prior art date
Application number
KR1019950052637A
Other languages
Korean (ko)
Other versions
KR0170479B1 (en
Inventor
박병선
이진희
윤형섭
양전욱
김기홍
박철순
Original Assignee
양승택
한국전자통신연구원
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 양승택, 한국전자통신연구원 filed Critical 양승택
Priority to KR1019950052637A priority Critical patent/KR0170479B1/en
Publication of KR970054538A publication Critical patent/KR970054538A/en
Application granted granted Critical
Publication of KR0170479B1 publication Critical patent/KR0170479B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

본 발명은 T-형 게이트 형성방법에 관한 것으로서, 반도체 기판 상에 감광막을 도포하고 소정 부분이 중첩되도록 동일한 마스크를 이동시키면서 파장이 짧은 자외선으로 2번 노광시키고 현상하여 T-형의 개구를 형성하는 공정과, 상기 감광막에 실란 용액을 선택적으로 확산시켜 부피 팽창시키는 공정과, 상술한 구조의 전 표면에 금속을 증착하여 개구 내에 반도체 기판과 접촉되는 T-형의 게이트 전극을 형성하는 공정과, 상기 감광막을 제거하는 공정을 구비한다.The present invention relates to a method of forming a T-type gate, wherein a photosensitive film is coated on a semiconductor substrate, and the same mask is moved to overlap a predetermined portion and exposed twice with ultraviolet light having a short wavelength and developed to form a T-type opening. Forming a T-type gate electrode in contact with a semiconductor substrate in an opening by depositing a metal on the entire surface of the structure described above; The process of removing a photosensitive film is provided.

따라서, 해상력 한계 이하의 감광막 패턴을 형성할 수 있으며 재현성 및 균일도가 향상된다.Thus, a photosensitive film pattern below the resolution limit can be formed, and reproducibility and uniformity are improved.

Description

T-형 게이트 형성방법T-type gate formation method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도(a) 내지 (d)는 본 발명에 따른 T-형 게이트 형성방법을 나타내는 공정도.3 (a) to (d) are process drawings showing a T-type gate forming method according to the present invention.

Claims (3)

반도체 기판 상에 감광막을 도포하고 소정 부분이 중첩되도록 동일한 마스크를 이동시키면서 파장이 짧은 자외선으로 2번 노광시키고 현상하여 T-형의 개구를 형성하는 공정과, 상기 감광막에 실란 용액을 선택적으로 확산시켜 부피 팽창시키는 공정과, 상술한 구조의 전 표면에 금속을 증착하여 개구 내에 반도체 기판과 접촉되는 T-형의 게이트 전극을 형성하는 공정과, 상기 감광막을 제거하는 공정을 구비하는 T-형 게이트 형성방법.Applying a photoresist film on a semiconductor substrate and moving the same mask so that a predetermined portion overlaps, and exposing and developing twice with ultraviolet light having a short wavelength to form a T-type opening; and selectively spreading a silane solution on the photoresist film. Forming a T-type gate electrode having a volume expansion step, depositing a metal on the entire surface of the above-described structure to form a T-type gate electrode in contact with the semiconductor substrate, and removing the photosensitive film. Way. 제1항에 있어서, 상기 감광막이 포지티브형인 T-형 게이트 형성방법.The method of claim 1, wherein the photoresist is positive. 제1항에 있어서, 상기 감광막을 실란 용액으로 확산시키기 전에 자외선으로 전면 노광하여 노광 부분과 비노광 부분으로 한정하는 공정을 더 구비하는 T-형 게이트 형성방법.The T-type gate forming method according to claim 1, further comprising a step of totally exposing the photosensitive film to ultraviolet light and diffusing it to an exposed portion and a non-exposed portion before diffusing the silane solution. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950052637A 1995-12-20 1995-12-20 Method for forming fine t-gate KR0170479B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950052637A KR0170479B1 (en) 1995-12-20 1995-12-20 Method for forming fine t-gate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950052637A KR0170479B1 (en) 1995-12-20 1995-12-20 Method for forming fine t-gate

Publications (2)

Publication Number Publication Date
KR970054538A true KR970054538A (en) 1997-07-31
KR0170479B1 KR0170479B1 (en) 1999-02-01

Family

ID=19441819

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950052637A KR0170479B1 (en) 1995-12-20 1995-12-20 Method for forming fine t-gate

Country Status (1)

Country Link
KR (1) KR0170479B1 (en)

Also Published As

Publication number Publication date
KR0170479B1 (en) 1999-02-01

Similar Documents

Publication Publication Date Title
KR970054538A (en) T-type gate formation method
KR970013040A (en) Semiconductor device manufacturing method
KR970008372A (en) Fine Pattern Formation Method of Semiconductor Device
KR970008364A (en) Fine pattern formation method
KR0139578B1 (en) Photoresist patterning method by lithography process
KR970077296A (en) Etching method of aluminum thin film
KR970016754A (en) Method of manufacturing mask for semiconductor device
KR970051898A (en) Pattern Forming Method of Semiconductor Device
KR960002592A (en) Manufacturing method of semiconductor device
KR950025484A (en) Method of forming chrome pattern of mask for semiconductor manufacturing
KR970003523A (en) Contact hole formation method of semiconductor device
KR910001460A (en) How to Improve Sidewall Profile of Photoresist
KR970003415A (en) Method of Forming Photosensitive Film Pattern on Semiconductor Substrate
KR950001893A (en) Ultra-fine contact hole formation method
KR950024261A (en) Rim type phase inversion mask and manufacturing method thereof
KR970054993A (en) Partial diffraction grating formation method
KR970013064A (en) Micro pattern formation method of semiconductor device
KR950021040A (en) Manufacturing Method of Semiconductor Device
KR950014974A (en) Manufacturing Method of Semiconductor Device
KR960039161A (en) Pattern Forming Method in Manufacturing Semiconductor Device
KR970051843A (en) Method of forming photoresist pattern of semiconductor device
KR950001355A (en) Manufacturing method of color filter
KR910001900A (en) Method of adjusting profile of polymer layer of semiconductor device
KR19980052471A (en) Manufacturing Method of Semiconductor Device
KR950027921A (en) Mask manufacturing method for semiconductor

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20070919

Year of fee payment: 10

LAPS Lapse due to unpaid annual fee