KR960039161A - Pattern Forming Method in Manufacturing Semiconductor Device - Google Patents

Pattern Forming Method in Manufacturing Semiconductor Device Download PDF

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Publication number
KR960039161A
KR960039161A KR1019950009819A KR19950009819A KR960039161A KR 960039161 A KR960039161 A KR 960039161A KR 1019950009819 A KR1019950009819 A KR 1019950009819A KR 19950009819 A KR19950009819 A KR 19950009819A KR 960039161 A KR960039161 A KR 960039161A
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South Korea
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region
target layer
thickness
etching
forming
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KR1019950009819A
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Korean (ko)
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KR0147468B1 (en
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윤석영
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문정환
엘지반도체 주식회사
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Publication of KR0147468B1 publication Critical patent/KR0147468B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)

Abstract

본 발명은 반도체장치 제조시의 패턴 형성방법에 관한 것으로, 사진식각공정에 의해 두께가 일정하지 않은 식각대상층은 식각하여 패터닝하기 위한 것이다. 본 발명은 기판상에 상대적으로 두께가 얇은 제1영역과 상대적으로 두께가 두꺼운 제2영역으로 이루어진 식각대상층을 형성하는 단계와, 상기 식각대상층상에 감광막을 도포하는 단계, 상기 감광막을 선택적으로 노광 및 현상하여 상기 식각대상층의 제2영역상에서는 상기 식각대상층을 선택적으로 노출시키는 완전한 형태를 갖고, 상기 식각대상층의 제1영역상에서는 노광된 부분의 하부에 소정두께만큼 잔류된 형태를 갖는 소정의 감광막패턴을 형성하는 단계, 및 상기 감광막패턴을 마스크로 이용하여 상기 식각대상층을 식각하여 소정의 패턴을 형성하는 단계로 이루어지는 반도체장치 제조시의 패턴 형성방법을 제공한다.The present invention relates to a method of forming a pattern in manufacturing a semiconductor device, and to etching and patterning an etch target layer whose thickness is not constant by a photolithography process. The present invention provides a method for forming an etching target layer comprising a first region having a relatively thin thickness and a second region having a relatively thick thickness, applying a photoresist film on the etching target layer, and selectively exposing the photoresist film. And a predetermined photoresist pattern having a form in which the etching target layer is selectively exposed on the second region of the etch target layer, and has a shape remaining on the first region of the etch target layer by a predetermined thickness below the exposed portion. And forming a predetermined pattern by etching the etch target layer using the photoresist pattern as a mask.

Description

반도체장치 제조시의 패턴 형성방법Pattern Forming Method in Manufacturing Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명에 의한 패턴 형성방법을 도시한 도면.2 is a view showing a pattern forming method according to the present invention.

Claims (8)

기판상에 상대적으로 두께가 얇은 제1영역과 상대적으로 두께가 두꺼운 제2영역으로 이루어진 식각대상층을 형성하는 단계와, 상기 식각대상층상에 감광막을 도포하는 단계, 상기 감광막을 선택적으로 노광 및 형상하여 상기 식각대상층의 제2영역상에서는 상기 식각대상층을 선택적으로 노출시키는 완전한 상태를 갖고, 상기 식각대상층의 제1영역상에서는 노광된 부분이 하부에 소정두께만큼 잔류된 형태를 갖는 소정의 감광막패턴을 형성하는 단계, 및 상기 감광막패턴을 마스크로 이용하여 상기 식각대상층을 식각하여 소정의 패턴을 형성하는 단계로 이루어지는 것을 특징으로 하는 반도체장치 제조시의 패턴 형성방법.Forming an etch target layer comprising a relatively thin first region and a relatively thick second region on a substrate, applying a photosensitive film on the etch target layer, and selectively exposing and shaping the photosensitive film. Forming a predetermined photoresist pattern having a form in which the etch target layer is selectively exposed on the second region of the etch target layer, and an exposed portion of the etch target layer having a predetermined thickness remaining in the lower portion of the etch target layer; And forming a predetermined pattern by etching the etch target layer using the photoresist pattern as a mask. 제1항에 있어서, 상기 감광막패턴은 부분적으로 반투과영역을 갖는 마스크를 이용한 노광 및 현상공정에 의해 형성하는 것을 특징으로 하는 반도체장치 제조시의 패턴 형성방법.The method of forming a semiconductor device according to claim 1, wherein the photosensitive film pattern is formed by an exposure and development process using a mask partially having a transflective region. 제2항에 있어서, 상기 마스크는 투명한 기판에 형성된 패턴구성을 위한 마스킹층으로 이루어진 마스킹영역과, 빛을 투과시키는 투과영역, 빛을 반투시키는 반투과영역으로 구성하는 것을 특징으로 하는 반도체장치제조시의 패턴 형성방법.The semiconductor device of claim 2, wherein the mask comprises a masking area formed of a masking layer for forming a pattern formed on a transparent substrate, a transmission area for transmitting light, and a semi-transmissive area for transmitting light. Pattern formation method. 제3항에 있어서, 상기 반투과영역은 상기 식각대상층의 제1영역상의 상기 감광막영역을 노광시키기 위해 이에 상당하는 영역임을 특징으로 하는 반도체 장치 제조시의 패턴 형성방법.The method of claim 3, wherein the transflective region is a region corresponding to the photosensitive film region on the first region of the etching target layer. 제3항에 있어서, 상기 반투과영역은 상기 마스킹층을 이루는 물질의 투과율과 다른 투과율을 갖는 물질을 상기 투명기판위에 증착하여 형성하는 것을 특징으로 하는 반도체 장치 제조시의 패턴 형성방법.The method of claim 3, wherein the semi-transmissive region is formed by depositing a material having a transmittance different from that of the material forming the masking layer on the transparent substrate. 제3항에 있어서, 상기 반투과영역은 상기 마스킹층을 이루는 물질을 상기 마스킹영역에 형성된 마스킹의 두께와는 다른 두께로 증착하여 형성하는 것을 특징으로 하는 반도체장치 제조시의 패턴 형성방법.The method of claim 3, wherein the semi-transmissive region is formed by depositing a material constituting the masking layer to a thickness different from a thickness of masking formed in the masking region. 제3항에 있어서, 상기 반투과영역은 상기 식각대상층의 제1영역과 제2영역의 두께차와 식각대상층의 식각율에 대한 상기 감광막의 식각율등을 고려하여 이에 상응하는 투과율을 갖도록 형성하는 것을 특징으로 하는 반도체장치 제조시의 패턴 형성방법.The method of claim 3, wherein the semi-transmissive region is formed to have a transmittance corresponding to the difference in thickness between the first region and the second region of the etching target layer and the etching rate of the photoresist with respect to the etching rate of the etching target layer. The pattern formation method at the time of manufacturing a semiconductor device characterized by the above-mentioned. 제1항에 있어서, 상기 식각대상층이 제1영역상에서 소정두께만큼 잔류된 형태를 갖는 상기 감광막패턴의 상기 잔류되는 두께는 상기 식각대상층을 식각하는 단계에서 상기 제2영역의 식각대상층의 두께가 상기 제1영역의 식각대상층 두께만큼 남을때까지 식각되는 동안 식각되어 제거될 수 있는 두께임을 특징으로 하는 반도체장치 제조시의 패턴 형성방법.2. The etching target layer of claim 1, wherein the remaining thickness of the photoresist pattern having the form in which the etching target layer remains by a predetermined thickness on the first region is equal to the thickness of the etching target layer in the second region. A method of forming a pattern in manufacturing a semiconductor device, characterized in that the thickness can be etched and removed while being etched until the thickness of the etch target layer of the first region remains. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950009819A 1995-04-25 1995-04-25 Method for forming pattern during manufacturing semiconductor device KR0147468B1 (en)

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KR960039161A true KR960039161A (en) 1996-11-21
KR0147468B1 KR0147468B1 (en) 1998-11-02

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114488703A (en) * 2021-12-10 2022-05-13 武汉新芯集成电路制造有限公司 Method for determining etching scheme, test mask plate and etching system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114488703A (en) * 2021-12-10 2022-05-13 武汉新芯集成电路制造有限公司 Method for determining etching scheme, test mask plate and etching system
CN114488703B (en) * 2021-12-10 2024-04-12 武汉新芯集成电路制造有限公司 Determination method of etching scheme, test mask plate and etching system

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KR0147468B1 (en) 1998-11-02

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