KR970003523A - Contact hole formation method of semiconductor device - Google Patents

Contact hole formation method of semiconductor device Download PDF

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Publication number
KR970003523A
KR970003523A KR1019950019104A KR19950019104A KR970003523A KR 970003523 A KR970003523 A KR 970003523A KR 1019950019104 A KR1019950019104 A KR 1019950019104A KR 19950019104 A KR19950019104 A KR 19950019104A KR 970003523 A KR970003523 A KR 970003523A
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KR
South Korea
Prior art keywords
contact hole
forming
mask
layer
semiconductor device
Prior art date
Application number
KR1019950019104A
Other languages
Korean (ko)
Other versions
KR100365751B1 (en
Inventor
이철승
이희목
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950019104A priority Critical patent/KR100365751B1/en
Publication of KR970003523A publication Critical patent/KR970003523A/en
Application granted granted Critical
Publication of KR100365751B1 publication Critical patent/KR100365751B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

본 발명은 서로 다른 단차부위에서 발생되는 콘택홀 폭의 불균일을 방지하기 위한 반도체 소자의 콘택홀 형성방법에 관한 것으로, 단차가 발생된 하지층의 전체 상부에 감광막을 도포한 다음, 콘택형성용 마스크를 이용한 포토리소그래피 공정으로 콘택홀 영역의 상기 하지층을 노출시키는 제1단계; 상기 제1단계에 의한 구조의 전체 상부에 반사 방지층을 형성하는 제2단계; 상기 수용성 반사방지층상에 감광막을 도포하는 제3단계; 및 상대적으로 얕은 단차영역의 상기 감광막을 리플로우시키는 제4단계를 포함하여 이루어지는 것을 특징으로 한다.The present invention relates to a method for forming a contact hole in a semiconductor device for preventing a nonuniformity of contact hole widths generated at different stepped portions. The present invention provides a contact forming mask after applying a photoresist to an entire upper layer of a stepped layer. A first step of exposing the underlayer in the contact hole region by a photolithography process; A second step of forming an anti-reflective layer over the entire structure of the first step; Applying a photoresist film on the water soluble antireflection layer; And a fourth step of reflowing the photosensitive film in a relatively shallow stepped region.

Description

반도체 소자의 콘택홀 형성방법Contact hole formation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제2C도는 본 발명의 일 실시예에 따른 콘택홀 형성과정을 나타내는 도면도.2A through 2C are diagrams illustrating a process of forming a contact hole according to an embodiment of the present invention.

Claims (4)

반도체 소자 제조공정 중 단차가 발생된 부위에 감광막 패턴을 이용한 콘택홀 형성방법에 있어서, 단차가 발생된 하지층의 전체 상부에 감광막을 도포한 다음, 콘택 형성용 마스크를 이용한 포토리소그래피 공정으로 콘택홀 영역의 상기 하지층을 노출시키는 제1단계; 상기 제1단계에 의한 구조의 전체 상부에 반사방지층을 형성하는 제2단계; 상기 수용성 반사방지층 상에 감광막을 도포하는 제3단계; 및 상대적으로 얕은 단차영역의 상기 감광막을 리플로우시키는 제4단계를 포함하여 이루어지는 것을 특징으로 하는 콘택홀 형성방법.In the method for forming a contact hole using a photoresist pattern on a portion where a step occurs in a semiconductor device manufacturing process, the photoresist is applied to the entire upper part of the base layer where the step is generated, and then the contact hole is formed by a photolithography process using a contact forming mask. Exposing the underlying layer of a region; A second step of forming an anti-reflective layer over the entire structure of the first step; Applying a photoresist film on the water soluble antireflection layer; And a fourth step of reflowing the photosensitive film in a relatively shallow stepped region. 제1항에 있어서,상기 제4단계는 상대적으로 얕은 단차영역이 투광 처리된 마스크를 이용하여 노광한 다음, 현상하는 단계와 하드 베이크를 실시하는 단계를 포함하여 이루어지는 것을 특징으로 하는 콘택홀 형성방법.The method of claim 1, wherein the fourth step comprises exposing a relatively shallow stepped area using a light-transmitted mask, and then developing and performing hard bake. . 제1항 또는 제2항에 있어서, 상기 반사방지층은 수용성 물질로 이루어지는 것을 특징으로 하는 콘택홀 형성방법.The method of claim 1 or 2, wherein the anti-reflection layer is formed of a water-soluble material. 제2항에 있어서, 상기 제4단계의 마스크는 상기 상대적으로 얕은 단차영역이 크롬 처리된 마스크인 것을 특징으로 하는 콘택홀 형성방법.The method of claim 2, wherein the mask of the fourth step is a mask in which the relatively shallow stepped region is chromed. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950019104A 1995-06-30 1995-06-30 Method for forming contact hole in semiconductor device KR100365751B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950019104A KR100365751B1 (en) 1995-06-30 1995-06-30 Method for forming contact hole in semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950019104A KR100365751B1 (en) 1995-06-30 1995-06-30 Method for forming contact hole in semiconductor device

Publications (2)

Publication Number Publication Date
KR970003523A true KR970003523A (en) 1997-01-28
KR100365751B1 KR100365751B1 (en) 2003-03-06

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KR1019950019104A KR100365751B1 (en) 1995-06-30 1995-06-30 Method for forming contact hole in semiconductor device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100555463B1 (en) * 1999-01-18 2006-03-03 삼성전자주식회사 Method for flowering photoresist

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100555463B1 (en) * 1999-01-18 2006-03-03 삼성전자주식회사 Method for flowering photoresist

Also Published As

Publication number Publication date
KR100365751B1 (en) 2003-03-06

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