KR970054512A - Method of manufacturing thin film transistor - Google Patents

Method of manufacturing thin film transistor Download PDF

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Publication number
KR970054512A
KR970054512A KR1019950064411A KR19950064411A KR970054512A KR 970054512 A KR970054512 A KR 970054512A KR 1019950064411 A KR1019950064411 A KR 1019950064411A KR 19950064411 A KR19950064411 A KR 19950064411A KR 970054512 A KR970054512 A KR 970054512A
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South Korea
Prior art keywords
conductive film
film
gate
gate oxide
thin film
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KR1019950064411A
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Korean (ko)
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KR100196503B1 (en
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권성우
남종완
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김주용
현대전자산업 주식회사
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Publication of KR970054512A publication Critical patent/KR970054512A/en
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Publication of KR100196503B1 publication Critical patent/KR100196503B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)

Abstract

본 발명은 박막트랜지스터 제조 방법에 있어서, 제1전도막, 게이트 산화막 및 제2전도막을 차례로 형성하고 게이트 마스크를 사용하여 상기 제2전도막, 상기 게이트 산화막 및 상기 제1전도막을 차례로 식각하여 패터닝 하되, 게이트 부위에서 박막트랜지스터의 역만큼 이격된 부위의 드레인 부위에도 패턴을 형성하는 단계; 전체구조 상부에 절연막을 형성하고 다시 전면 에치백하여 상기 패터닝된 제2전도막, 게이트 산화막 및 제1전도막 측벽에 절연막을 형성하는 단계; 드레인 부위의 제1전도막 패턴의 소정 부위가 드러나도록 마스크 작업을 통해 제2전도막 및 게이트 산화막을 선택 식각하는 단계; 전체구조 상부에 제3전도막을 형성하는 단계; 게이트와 오버랩되는 제3전도막을 선택 식각하는 단계; 이온주입에 의해 제3전도막의 소정부위에 소오스가 정의되고, 게이트 상부에 오버랩 되어 형성된 제2전도막에 오프-셋 영역으로 정의되고, 제1전도막이 서로 이격되는 지역에 형성된 제3전도막에 오프-셋 영역으로 정의되며, 제1내지 제3전도막이 서로 접속된 부위에 드레인을 정의하는 단계를 포함하는 것을 특징으로 하는 박막트랜지스터 제조 방법에 관한 것으로, 종래의 박막트랜지스터 제조 방법과는 달리 박막트랜지스터의 게이트 산화막 형성 후, 곧 바로 채널 폴리실리콘막을 증착한 뒤 마스크 작업을 함으로써, 게이트 산화막의 특성 저하를 방지하며, 박막트랜지스터의 소오스/드레인의 두께를 채널과 달리 임의로 조정가능함으로 소오스/드레인의 저항을 낮추어 박막트랜지스터의 온 전류를 향상시킨다.In the method of manufacturing a thin film transistor, the first conductive film, the gate oxide film, and the second conductive film are sequentially formed, and the second conductive film, the gate oxide film, and the first conductive film are sequentially etched and patterned using a gate mask. Forming a pattern on the drain portion of the portion of the gate spaced apart from the gate by the inverse of the thin film transistor; Forming an insulating film on the entire structure and etching back the entire surface to form an insulating film on the sidewalls of the patterned second conductive film, the gate oxide film, and the first conductive film; Selectively etching the second conductive film and the gate oxide film through a mask operation so that a predetermined portion of the first conductive film pattern of the drain portion is exposed; Forming a third conductive film on the entire structure; Selectively etching the third conductive film overlapping the gate; The source is defined at a predetermined portion of the third conductive film by ion implantation, the second conductive film is formed as an off-set region in the second conductive film formed by overlapping the upper portion of the gate, and the third conductive film is formed in an area where the first conductive film is spaced apart from each other. Defined as the off-set region, and comprises a step of defining a drain in the first to third conductive film is connected to each other, characterized in that the thin film transistor manufacturing method, unlike the conventional thin film transistor manufacturing method Immediately after the gate oxide film is formed in the transistor, the channel polysilicon film is deposited and masked to prevent deterioration of the characteristics of the gate oxide film, and the thickness of the source / drain of the thin film transistor can be arbitrarily adjusted, unlike the channel. Lowering the resistance improves the on-state current of the thin film transistor.

Description

박막트랜지스터 제조 방법Method of manufacturing thin film transistor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 일실시예에 따른 박막트랜스터 제조 공정도.1 is a thin film transistor manufacturing process according to an embodiment of the present invention.

Claims (1)

박막트랜지스터 제조 방법에 있어서, 제1전도막, 게이트 산화막 및 제2전도막을 차례로 형성하고 게이트 마스크를 사용하여 상기 제2전도막, 상기 게이트 산화막 및 상기 제1전도막을 차례로 식각하여 패터닝 하되, 게이트 부위에서 박막트랜지스터의 오프-셋 영역만큼 이격된 부위의 드레인 부위에도 패턴을 형성하는 단계; 전체구조 상부에 절연막을 형성하고 다시 전면 에치백하여 상기 패터닝된 제2전도막, 게이트 산화막 및 제1전도막 측벽에 절연막을 형성하는 단계; 드레인 부위의 제1전도막 패턴의 소정 부위가 드러나도록 마스크 작업을 통해 제2전도막 및 게이트 산화막을 선택 식각하는 단계; 전체구조 상부에 제3전도막을 형성하는 단계; 게이트와 오버랩되는 제3전도막을 선택 식각하는 단게; 이온주입에 의해 제3전도막의 소정부위에 소오스가 정의되고, 게이트 상부에 오버랩 되어 형성된 제2전도막에 채널이 정의되고, 제1전도막이 서로 이격되는 지역에 형성된 제3전도막이 오프-셋 영역으로 정의되며, 제2전도막과 제3전도막이 서로 콘택된 부위에 드레인을 정의하는 단계를 포함하는 것을 특징으로 하는 박막트랜지스터 제조 방법.In the method of manufacturing a thin film transistor, a first conductive film, a gate oxide film, and a second conductive film are sequentially formed and patterned by sequentially etching the second conductive film, the gate oxide film, and the first conductive film by using a gate mask. Forming a pattern on the drain portion of the portion spaced apart by the off-set region of the thin film transistor in the first embodiment; Forming an insulating film on the entire structure and etching back the entire surface to form an insulating film on the sidewalls of the patterned second conductive film, the gate oxide film, and the first conductive film; Selectively etching the second conductive film and the gate oxide film through a mask operation so that a predetermined portion of the first conductive film pattern of the drain portion is exposed; Forming a third conductive film on the entire structure; Selectively etching the third conductive film overlapping the gate; The source is defined at a predetermined portion of the third conductive film by ion implantation, the channel is defined in the second conductive film formed by overlapping the gate, and the third conductive film is formed in an area where the first conductive film is spaced apart from each other. And defining a drain at a portion where the second conductive film and the third conductive film are in contact with each other. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950064411A 1995-12-29 1995-12-29 Method of fabricating a thin film transistor KR100196503B1 (en)

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KR1019950064411A KR100196503B1 (en) 1995-12-29 1995-12-29 Method of fabricating a thin film transistor

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KR970054512A true KR970054512A (en) 1997-07-31
KR100196503B1 KR100196503B1 (en) 1999-07-01

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US7655127B2 (en) * 2006-11-27 2010-02-02 3M Innovative Properties Company Method of fabricating thin film transistor

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