KR970054521A - Structure and manufacturing method of thin film transistor - Google Patents

Structure and manufacturing method of thin film transistor Download PDF

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Publication number
KR970054521A
KR970054521A KR1019950067226A KR19950067226A KR970054521A KR 970054521 A KR970054521 A KR 970054521A KR 1019950067226 A KR1019950067226 A KR 1019950067226A KR 19950067226 A KR19950067226 A KR 19950067226A KR 970054521 A KR970054521 A KR 970054521A
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South Korea
Prior art keywords
gate electrode
forming
insulating film
active layer
drain region
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KR1019950067226A
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Korean (ko)
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KR100209743B1 (en
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박성계
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문정환
Lg 반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H01L29/78624—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile the source and the drain regions being asymmetrical
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)

Abstract

본 발명은 박막 트랜지스터 구조 및 제조방법에 관한 것으로 특히, 누선전류를 감소시키는데 적합하도록한 박막 트랜지스터에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to thin film transistor structures and manufacturing methods, and more particularly to thin film transistors adapted to reduce leakage currents.

따라서, 본 발명의 박막 트랜지스터의 구조는 기판, 기판위에 형성되는 제1절연막, 상기 제1절연막위에 돌출부를 갖는 게이트 전극, 상기 게이트 전극을 포함한 기판 전면에 형성되는 제2절연막, 상기 제2절연막위에 게이트 전극의 돌출부를 포함하고, 상기 게이트 전극과 수직으로 교차되도록 형성되는 활성층, 상기 게이트 전극에 오버랩 되고 상기 게이트 전극을 돌출부에 오프셋 되도록 상기 활성층에 형성되는 소오소/드레인 영역, 상기 소오소/드레인 영역에 콘택홀을 갖고 상기 활성층 위에 형성되는 제3절연막, 상기 소오소/드레인 영역에 연결되도록 콘택홀에 형성되는 메탈을 포함하여 구성되고, 본 발명의 박막 트랜지스터의 제조방법은 기판위에 제1절연막을 형성하는 단계, 상기 제1절연막위에 돌출부를 갖는 게이트 전극을 형성하는 단계, 상기 게이트 전극을 포함한 기판 전면에 제2절연막을 형성하는 단계, 상기 제2절연막위에 게이트 전극의 돌출부를 포함하고 상기 게이트 전극과 수직으로 교차하도록 활성층을 형성하는 단계, 상기 활성층위에 감광막을 도포하고 패터닝하여 소오소/드레인 영역을 형성하는 단계, 상기 활성층위에 제3절연막을 형성하고, 상기 소오소/드레인 영역이 노출되도록 콘택홀을 형성하는 단계, 상기 소오소/드레인 영역에 연결되도록 상기 콘택홀에 메탈을 형성하는 단계를 포함하여 이루어진다.Therefore, the structure of the thin film transistor of the present invention includes a substrate, a first insulating film formed on the substrate, a gate electrode having a protrusion on the first insulating film, a second insulating film formed on the entire surface of the substrate including the gate electrode, and the second insulating film. An active layer including a protrusion of a gate electrode, the active layer formed to vertically cross the gate electrode, a ososo / drain region formed in the active layer to overlap the gate electrode and to offset the gate electrode to the protrusion, and the ososo / drain region And a third insulating film formed on the active layer with a contact hole in a region, and a metal formed in the contact hole so as to be connected to the source / drain regions. The method of manufacturing a thin film transistor of the present invention includes a first insulating film formed on a substrate. Forming a gate electrode having a protrusion on the first insulating layer, and Forming a second insulating film on the entire surface of the substrate including the gate electrode; forming an active layer including a protrusion of the gate electrode on the second insulating film and vertically crossing the gate electrode; applying and patterning a photosensitive film on the active layer Forming a source / drain region, forming a third insulating layer on the active layer, forming a contact hole to expose the source / drain region, and forming a metal in the contact hole so as to be connected to the source / drain region It comprises a step of forming.

따라서, 채널영역의 누설전류를 감소시킬 수 있다.Thus, leakage current in the channel region can be reduced.

Description

박막 트랜지스터의 구조 및 제조방법Structure and manufacturing method of thin film transistor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명의 박막 트랜지스터의 평면도 및 단면도,3 is a plan view and a cross-sectional view of a thin film transistor of the present invention;

제4도는 제3도의 A-A' 및 B-B'선상의 본 발명의 박막 트랜지스터 제조공정 단면도.4 is a cross-sectional view of the manufacturing process of the thin film transistor of the present invention taken along line A-A 'and B-B' of FIG.

Claims (3)

기판, 기판위에 형성되는 제1절연막, 상기 제1절연막위에 돌출부를 갖는 게이트 전극, 상기 게이트 전극을 포함한 기판 전면에 형성되는 제2절연막, 상기 제2절연막위에 게이트 전극의 돌출부를 포함하고, 상기 게이트 전극과 수직으로 교차되도록 형성되는 활성층, 상기 게이트 전극에 오버랩 되고 상기 게이트 전극의 돌출부에 오프셋 되도록 상기 활성층에 형성되는 소오소/드레인 영역, 상기 소오소/드레인 영역에 콘택홀을 갖고 상기 활성층 위에 형성되는 제3절연막, 상기 소오소/드레인 영역에 연결되도록 콘택홀에 형성되는 메탈을 포함하여 구성됨을 특징으로 하는 박막 트랜지스터의 구조.A substrate, a first insulating film formed on the substrate, a gate electrode having a protrusion on the first insulating film, a second insulating film formed on an entire surface of the substrate including the gate electrode, and a protrusion of the gate electrode on the second insulating film, wherein the gate An active layer formed to intersect the electrode perpendicularly to the electrode, a source / drain region formed in the active layer to overlap the gate electrode and offset the protrusion of the gate electrode, and a contact hole in the source / drain region and formed on the active layer And a metal formed in the contact hole so as to be connected to the source / drain region. 제1항에 있어서, 상기 소오스 영역은 드레인 영역보다 채널 폭이 넓은 것을 특징으로 하는 박막 트랜지스터의 구조.The thin film transistor structure of claim 1, wherein the source region has a wider channel width than the drain region. 기판위에 제1절연막을 형성하는 단계, 상기 제1절연막위에 돌출부를 갖는 게이트 전극을 형성하는 단계, 상기 게이트 전극을 포함한 기판 전면에 제2절연막을 형성하는 단계, 상기 제2절연막위에 게이트 전극의 돌출부를 포함하고 상기 게이트 전극과 수직으로 교차하도록 활성층을 형성하는 단계, 상기 활성층위에 감광막을 도포하고 패터닝 하여 소오소/드레인 영역을 형성하는 단계, 상기 활성층위에 제3절연막을 형성하고, 상기 소오소/드레인 영역이 노출되도록 콘택홀을 형성하는 단계, 상기 소오소/드레인 영역에 연결되도록 상기 콘택홀에 메탈을 형성하는 단계를 포함하여 이루어짐을 특징으로 하는 박막 트랜지스터 제조방법.Forming a first insulating film on the substrate, forming a gate electrode having a protrusion on the first insulating film, forming a second insulating film on the entire surface of the substrate including the gate electrode, and protruding portion of the gate electrode on the second insulating film. Forming an active layer to vertically intersect the gate electrode, applying and patterning a photoresist film on the active layer to form a source / drain region, forming a third insulating layer on the active layer, and Forming a contact hole to expose a drain region, and forming a metal in the contact hole to be connected to the source / drain region. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950067226A 1995-12-29 1995-12-29 A thin film transistor structure and a method of fabricating the same KR100209743B1 (en)

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KR1019950067226A KR100209743B1 (en) 1995-12-29 1995-12-29 A thin film transistor structure and a method of fabricating the same

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KR100209743B1 KR100209743B1 (en) 1999-07-15

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