KR970053176A - Bonding pad formation method of semiconductor device - Google Patents

Bonding pad formation method of semiconductor device Download PDF

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Publication number
KR970053176A
KR970053176A KR1019950054624A KR19950054624A KR970053176A KR 970053176 A KR970053176 A KR 970053176A KR 1019950054624 A KR1019950054624 A KR 1019950054624A KR 19950054624 A KR19950054624 A KR 19950054624A KR 970053176 A KR970053176 A KR 970053176A
Authority
KR
South Korea
Prior art keywords
semiconductor device
bonding
bonding pad
forming
koh solution
Prior art date
Application number
KR1019950054624A
Other languages
Korean (ko)
Other versions
KR100220243B1 (en
Inventor
박상훈
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950054624A priority Critical patent/KR100220243B1/en
Publication of KR970053176A publication Critical patent/KR970053176A/en
Application granted granted Critical
Publication of KR100220243B1 publication Critical patent/KR100220243B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

본 발명은 반도체 소자의 본딩 패드 형성방법에 관한 것으로, 특히, 반도체 소자의 본딩 패드 과정에서 본딩 결과를 정확히 예측할 수 있는 반도체 소자의 본딩 패드 형성방법에 관한 것으로, 본 발명은 반도체 소자의 금속 패드막의 오픈 공정 이후, KOH 용액에 결과물이 형성된 웨이퍼를 첨지하여, 그의 결과에 따라 본딩 패드 부위의 자연 산화막의 성장여부를 판별하므로써, 이후 진행되는 와이어 본딩 및 패키지 공정시 제조수율이 향상된다.The present invention relates to a method of forming a bonding pad of a semiconductor device, and more particularly, to a method of forming a bonding pad of a semiconductor device capable of accurately predicting a bonding result in a process of bonding pads of a semiconductor device. After the open process, the wafer on which the resultant is formed in the KOH solution is added, and the growth of the natural oxide film in the bonding pad region is determined according to the result, thereby improving the manufacturing yield during the subsequent wire bonding and packaging process.

Description

반도체 소자의 본딩 패드 형성방법Bonding pad formation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도 (가) 및 (나)는 본 발명에 따른 반도체 소자의 본딩 패드 형성방법을 설명하기 위한 도면.2A and 2B are views for explaining a method of forming a bonding pad of a semiconductor device according to the present invention.

Claims (3)

기본 전극이 구비된 반도체 기판부에 절연막을 형성하고, 금속 패드막을 형성한 다음, 절연 산화막을 형성하고, 소정 부분 식각하여 금속 패드막을 오픈하는 공정을 포함하는 반도체 소자의 본딩 패드 형성방법에 있어서, 상기 금속 패드막을 오픈시키는 단계이후, 상기 오픈된 금속 패드막이 형성된 웨이퍼를 KOH 용액에 침지하여 본딩 불량 여부를 판별하는 공정을 포함하는 것을 특징으로 하는 반도체 소자의 본딩 패드 형성방법.A method of forming a bonding pad for a semiconductor device, the method including forming an insulating film on a semiconductor substrate provided with a basic electrode, forming a metal pad film, forming an insulating oxide film, and etching the predetermined portion to open the metal pad film. And after the step of opening the metal pad film, immersing the wafer on which the open metal pad film is formed in a KOH solution to determine whether there is a defect in bonding. 제1항에 있어서, 상기 웨이퍼를 KOH 용액에 침지시키는 단계 이후, 반응이 이루어지지 않은 다이를 샘플링하여 추가로 식각하는 공정을 부가적으로 포함하는 것을 특징으로 하는 반도체 소자의 본딩 패드 형성방법.The method of claim 1, further comprising, after immersing the wafer in a KOH solution, sampling and further etching a die that has not been reacted. 제1항 또는 제2항에 있어서, 상기 KOH 용액에 침지하는 시간은 약 3 내지 10분간인 것을 특징으로 하는 반도체 소자의 본딩 패드 형성방법.The method of claim 1, wherein the time for immersion in the KOH solution is about 3 to 10 minutes. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950054624A 1995-12-22 1995-12-22 Bonding pad of semiconductor device KR100220243B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950054624A KR100220243B1 (en) 1995-12-22 1995-12-22 Bonding pad of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950054624A KR100220243B1 (en) 1995-12-22 1995-12-22 Bonding pad of semiconductor device

Publications (2)

Publication Number Publication Date
KR970053176A true KR970053176A (en) 1997-07-29
KR100220243B1 KR100220243B1 (en) 1999-09-15

Family

ID=19443196

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950054624A KR100220243B1 (en) 1995-12-22 1995-12-22 Bonding pad of semiconductor device

Country Status (1)

Country Link
KR (1) KR100220243B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100681676B1 (en) * 2005-12-01 2007-02-09 동부일렉트로닉스 주식회사 Method for forming pad in semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100681676B1 (en) * 2005-12-01 2007-02-09 동부일렉트로닉스 주식회사 Method for forming pad in semiconductor device

Also Published As

Publication number Publication date
KR100220243B1 (en) 1999-09-15

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