KR970052857A - Method for forming interlayer insulating film of semiconductor device - Google Patents

Method for forming interlayer insulating film of semiconductor device Download PDF

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Publication number
KR970052857A
KR970052857A KR1019950065682A KR19950065682A KR970052857A KR 970052857 A KR970052857 A KR 970052857A KR 1019950065682 A KR1019950065682 A KR 1019950065682A KR 19950065682 A KR19950065682 A KR 19950065682A KR 970052857 A KR970052857 A KR 970052857A
Authority
KR
South Korea
Prior art keywords
insulating film
interlayer insulating
semiconductor device
forming
forming interlayer
Prior art date
Application number
KR1019950065682A
Other languages
Korean (ko)
Other versions
KR100332117B1 (en
Inventor
최준기
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950065682A priority Critical patent/KR100332117B1/en
Publication of KR970052857A publication Critical patent/KR970052857A/en
Application granted granted Critical
Publication of KR100332117B1 publication Critical patent/KR100332117B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02312—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour
    • H01L21/02315—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 금속층간 절연막 형성 방법에 관한 것으로, 금속층의 부식 및 특성 저하를 방지하기 위하여 금속층간 절연막을 형성하기 전.후에 하부층의 표면을 HCl가스를 이용하여 플라즈마 처리하므로써 금속층에 존재하는 나트륨 이온 및 수분을 제거시킬 수 있다. 그러므로 금속층의 부식 및 특성 저하가 방지되어 소자의 전기적 특성이 향상될 수 있도록 한 반도체 소자의 금속층간 절연막 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an interlayer insulating film of a semiconductor device, and to prevent corrosion and deterioration of a metal layer. Sodium ions and moisture can be removed. Therefore, the present invention relates to a method for forming an insulating film between metal layers of a semiconductor device to prevent corrosion and deterioration of a metal layer and to improve electrical properties of the device.

Description

반도체 소자의 금속층간 절연막 형성 방법.A method of forming an interlayer insulating film of a semiconductor device.

내용없음No content

Claims (3)

반도체 소자의 금속층간 절연막 형성 방법에 있어서, 절연층이 형성된 실리콘 기판상에 금속층을 형성한 후 전체 상부면에 금속층간 절연막을 형성하되, 상기 금속층간 절연막을 형성하기 전.후에 하부층의 표면을 플라즈마 처리하는 것을 특징으로 하는 반도체 소자의 금속층간 절연막 형성 방법.In the method for forming an interlayer insulating film of a semiconductor device, after forming a metal layer on the silicon substrate on which the insulating layer is formed, an intermetallic insulating film is formed on the entire upper surface, but before and after forming the interlayer insulating film, the surface of the lower layer is plasma A method for forming an interlayer insulating film of a semiconductor device, characterized in that the treatment. 제1항에 있어서, 상기 금속층간 절연막은 350 내지 400℃의 온도 및 1.8 내지 2.8 Torr의 압력 상태에서 형성되는 것을 특징으로 하는 반도체 소자의 금속층간 절연막 형성 방법.The method of claim 1, wherein the interlayer insulating film is formed at a temperature of 350 to 400 ° C. and a pressure of 1.8 to 2.8 Torr. 제1항에 있어서, 상기 플라즈마 처리시 2 내지 3 SCCM의 HCl 가스가 3 내지 5초간 플로우되는 것을 특징으로 하는 반도체 소자의 금속층간 절연막 형성 방법.The method of claim 1, wherein HCl gas of 2 to 3 SCCM flows for 3 to 5 seconds during the plasma treatment. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950065682A 1995-12-29 1995-12-29 Method for fabricating intermetal dielectric of semiconductor device KR100332117B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950065682A KR100332117B1 (en) 1995-12-29 1995-12-29 Method for fabricating intermetal dielectric of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950065682A KR100332117B1 (en) 1995-12-29 1995-12-29 Method for fabricating intermetal dielectric of semiconductor device

Publications (2)

Publication Number Publication Date
KR970052857A true KR970052857A (en) 1997-07-29
KR100332117B1 KR100332117B1 (en) 2002-09-04

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950065682A KR100332117B1 (en) 1995-12-29 1995-12-29 Method for fabricating intermetal dielectric of semiconductor device

Country Status (1)

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KR (1) KR100332117B1 (en)

Also Published As

Publication number Publication date
KR100332117B1 (en) 2002-09-04

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