KR970052610A - Etching Method of Semiconductor Thin Film - Google Patents

Etching Method of Semiconductor Thin Film Download PDF

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Publication number
KR970052610A
KR970052610A KR1019950067343A KR19950067343A KR970052610A KR 970052610 A KR970052610 A KR 970052610A KR 1019950067343 A KR1019950067343 A KR 1019950067343A KR 19950067343 A KR19950067343 A KR 19950067343A KR 970052610 A KR970052610 A KR 970052610A
Authority
KR
South Korea
Prior art keywords
etching
tiw
thin film
semiconductor thin
bcl
Prior art date
Application number
KR1019950067343A
Other languages
Korean (ko)
Other versions
KR100206884B1 (en
Inventor
이상용
Original Assignee
문정환
Lg 반도체 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, Lg 반도체 주식회사 filed Critical 문정환
Priority to KR1019950067343A priority Critical patent/KR100206884B1/en
Publication of KR970052610A publication Critical patent/KR970052610A/en
Application granted granted Critical
Publication of KR100206884B1 publication Critical patent/KR100206884B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 박막의 식각방법에 관한 것으로, 포토 레지스트로 식각될 부분을 정의하는 공정과; 이후 E.C.R식각시에서 BCl3+SF6+N2가스를 이용하여 TiW를 식각하는 공정과; 이후 A-Si을 식각함으로써 식각이 완료되는데, FPGA제품의 앤티-퓨즈 필름으로 이용되는 TiW+A-Si 막질을 E.C.R.식각기에서 동시에 식각함으로써 A-Si의 프로파일을 유지하고 하부레이어의 손상없이 식각을 완료할 수 있다.The present invention relates to a method for etching a semiconductor thin film, the method comprising: defining a portion to be etched into a photoresist; Then etching TiW using BCl 3 + SF 6 + N 2 gas in ECR etching; Etching is then completed by etching A-Si.At the same time, the TiW + A-Si film used as an anti-fuse film of FPGA products is simultaneously etched in an ECR etcher to maintain the profile of A-Si and etch without damaging the underlying layer. You can complete

또한, TiW의 식각으로 인한 장치 및 소자의 메탈 오염을 방지할 수 있다.In addition, it is possible to prevent metal contamination of devices and devices due to the etching of TiW.

Description

반도체 박막의 식각방법Etching Method of Semiconductor Thin Film

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명에 따른 반도체 박막의 식각과정의 도시도.3 is a view showing an etching process of a semiconductor thin film according to the present invention.

Claims (3)

포토 레지스트로 식각될 부분을 정의하는 공정과; 이후 TiW를 식각하는 공정과; 이후 A-Si을 식각하는 공정으로 이루어지는 것을 특징으로 하는 반도체 박막의 식각방법.Defining a portion to be etched into the photoresist; Thereafter etching the TiW; Thereafter, the etching method of the semiconductor thin film comprising the process of etching A-Si. 제1항에 있어서, 상기 TiW와 A-Si는 E.C.R식각기에서 BCl3+SF6+N2가스를 이용하여 식각하는 것을 특징으로 하는 반도체 박막의 식각방법.The method of claim 1, wherein the TiW and A-Si are etched using BCl 3 + SF 6 + N 2 gas in an ECR etcher. 제2항에 있어서, 식각에 이용되는 BCl3+SF6+N2가스는 BCl3(40),SF6(25),N2(10)의 비율로 하고, 14mTorr의 기압과, 300mA의 전류와, 40w의 전력하에서 식각하는 것을 특징으로 하는 반도체 박막의 식각방법.The method of claim 2, wherein the BCl 3 + SF 6 + N 2 gas used for etching is a ratio of BCl 3 (40), SF 6 (25), N 2 (10), the atmospheric pressure of 14mTorr and the current of 300mA And etching under a power of 40 watts. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950067343A 1995-12-29 1995-12-29 Method for etching thin film of semiconductor KR100206884B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950067343A KR100206884B1 (en) 1995-12-29 1995-12-29 Method for etching thin film of semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950067343A KR100206884B1 (en) 1995-12-29 1995-12-29 Method for etching thin film of semiconductor

Publications (2)

Publication Number Publication Date
KR970052610A true KR970052610A (en) 1997-07-29
KR100206884B1 KR100206884B1 (en) 1999-07-01

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ID=19447669

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950067343A KR100206884B1 (en) 1995-12-29 1995-12-29 Method for etching thin film of semiconductor

Country Status (1)

Country Link
KR (1) KR100206884B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010045256A (en) * 1999-11-04 2001-06-05 박종섭 A method of improving an etch profile

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010045256A (en) * 1999-11-04 2001-06-05 박종섭 A method of improving an etch profile

Also Published As

Publication number Publication date
KR100206884B1 (en) 1999-07-01

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