KR970052276A - Method for forming contact hole in semiconductor device - Google Patents

Method for forming contact hole in semiconductor device Download PDF

Info

Publication number
KR970052276A
KR970052276A KR1019950051066A KR19950051066A KR970052276A KR 970052276 A KR970052276 A KR 970052276A KR 1019950051066 A KR1019950051066 A KR 1019950051066A KR 19950051066 A KR19950051066 A KR 19950051066A KR 970052276 A KR970052276 A KR 970052276A
Authority
KR
South Korea
Prior art keywords
film
contact hole
semiconductor device
forming
photoresist
Prior art date
Application number
KR1019950051066A
Other languages
Korean (ko)
Other versions
KR0163087B1 (en
Inventor
신유철
이주영
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950051066A priority Critical patent/KR0163087B1/en
Publication of KR970052276A publication Critical patent/KR970052276A/en
Application granted granted Critical
Publication of KR0163087B1 publication Critical patent/KR0163087B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

본 발명은 반도체장치의 콘택홀을 형성하는 방법으로서, 특히 고집적 반도체장치에서의 콘택홀을 미세하게 형성하는 방법에 관한 것이다. 콘택홀로 형성하고자 하는 막질의 일부를 경사지게 식각한 다음, 이방성 식각으로 상기의 막질을 제거하므로써, 콘택홀을 종래보다 적은 폭을 가지도록 형성하여 고집적화된 반도체장치를 제조하는 관련 기술을 확보하게 되고, 이에 따른 반도체장치의 품질을 향상시키고, 그의 수율을 높힐 수 있게 된다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a contact hole in a semiconductor device, and more particularly, to a method of finely forming a contact hole in a highly integrated semiconductor device. By partially etching the film to be formed as a contact hole and then removing the film by anisotropic etching, the contact hole is formed to have a smaller width than before, thereby securing a related technology for manufacturing a highly integrated semiconductor device. As a result, the quality of the semiconductor device can be improved, and the yield thereof can be increased.

Description

반도체장치의 콘택홀의 형성방법Method for forming contact hole in semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 제1실시예에 따라 콘택홀을 형성하는 공정들을 설명하기 위한 단면도.2 is a cross-sectional view for explaining a process of forming a contact hole according to the first embodiment of the present invention.

제3도는 본 발명의 제2실시예에 따라 콘택홀을 형성하는 공정들을 설명하기 위한 단면도.3 is a cross-sectional view for describing a process of forming a contact hole according to a second embodiment of the present invention.

Claims (3)

실리콘 기판(110)상에 제1산화막(120), 제1포토 레지스트막(130), 제2산화막(140), 제2포토 레지스트막(150)을 차례로 형성하는 공정과, 상기의 제2포토 레지스트막(150)을 소정의 패턴에 따라 패터닝하는 공정과, 상기의 패터닝된 제2포토 레지스트막(150)을 마스크로 하여 그 하부의 제2산화막(140)의 일부를 경사지게 식각하는 공정과, 상기의 남아 있는 제2산화막(140), 그 하부의 제1포토 레지스트막(130), 제1산화막(120)을 선택적으로 이방성 식각하여 기판(110)과의 콘택홀(160)을 형성하는 공정을 포함하는 것을 특징으로 하는 반도체장치의 콘택홀의 형성방법.Forming a first oxide film 120, a first photoresist film 130, a second oxide film 140, and a second photoresist film 150 on the silicon substrate 110 in sequence, and the second photoresist described above. Patterning the resist film 150 according to a predetermined pattern, using a patterned second photoresist film 150 as a mask, and etching a portion of the second oxide film 140 beneath it at an angle; Selectively anisotropically etching the remaining second oxide layer 140, the first photoresist layer 130, and the first oxide layer 120 to form a contact hole 160 with the substrate 110. Forming a contact hole of a semiconductor device comprising a. 실리콘 기판(110)상에 산화막(115), 폴리 실리콘막(125), 포토 레지스트막(135)을 차례로 형성하는 공정과, 상기의 포토 레지스트막(135)을 소정의 패턴에 따라 패터닝하는 공정과, 상기의 패터닝된 포토 레지스트막(135)을 포함하는 폴리 실리콘막(125)상에 저온 산화막을 형성하고, 이를 에치백하여 상기의 패터닝된 포토 레지스트막(135)의 측면에 스페이서(145)로 형성하는 공정과, 상기의 스페이서(145)를 마스크로 하여 그 하부의 폴리 실리콘막(125), 산화막(115)을 식각하여 기판(110)과의 콘택홀(160)을 형성하는 공정을 포함하는 것을 특징으로 하는 반도체장치의 콘택홀의 형성방법.Forming an oxide film 115, a polysilicon film 125, and a photoresist film 135 on the silicon substrate 110 in sequence; patterning the photoresist film 135 according to a predetermined pattern; A low temperature oxide film is formed on the polysilicon film 125 including the patterned photoresist film 135, and etched back to form a spacer 145 on a side surface of the patterned photoresist film 135. Forming the contact hole 160 with the substrate 110 by etching the polysilicon film 125 and the oxide film 115 below the spacer 145 as a mask. A method of forming a contact hole in a semiconductor device, characterized in that the. 제2항에 있어서, 상기의 저온 산화막은 LT-TEOS막인 것을 특징으로 하는 반도체장치의 콘택홀의 형성방법.3. The method of claim 2, wherein the low temperature oxide film is an LT-TEOS film. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950051066A 1995-12-16 1995-12-16 Method for forming contact hole in semiconductor device KR0163087B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950051066A KR0163087B1 (en) 1995-12-16 1995-12-16 Method for forming contact hole in semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950051066A KR0163087B1 (en) 1995-12-16 1995-12-16 Method for forming contact hole in semiconductor device

Publications (2)

Publication Number Publication Date
KR970052276A true KR970052276A (en) 1997-07-29
KR0163087B1 KR0163087B1 (en) 1999-02-01

Family

ID=19440820

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950051066A KR0163087B1 (en) 1995-12-16 1995-12-16 Method for forming contact hole in semiconductor device

Country Status (1)

Country Link
KR (1) KR0163087B1 (en)

Also Published As

Publication number Publication date
KR0163087B1 (en) 1999-02-01

Similar Documents

Publication Publication Date Title
KR940010205A (en) Contact hole formation method of highly integrated semiconductor device
KR970051945A (en) Manufacturing Method of Semiconductor Device
KR970052276A (en) Method for forming contact hole in semiconductor device
KR960026297A (en) Manufacturing method of fine pattern of semiconductor device
KR970054082A (en) Manufacturing Method of Semiconductor Device
KR940004836A (en) Contact hole formation method of semiconductor device
KR950027971A (en) Manufacturing method of fine pattern of semiconductor device
KR970060387A (en) Method for manufacturing semiconductor device
KR970018049A (en) Micro pattern formation method using auxiliary pattern method
KR970052600A (en) Manufacturing Method of Semiconductor Device
KR950021075A (en) Method for forming contact hole in semiconductor device
KR19980026093A (en) Method of forming fine pattern of semiconductor device
KR970052192A (en) Contact hole formation method of semiconductor device
KR970053443A (en) Method of forming device isolation region
KR970052397A (en) Manufacturing Method of Semiconductor Device
KR950021096A (en) Contact hole formation method of semiconductor device
KR970016758A (en) Micro pattern formation method using polymer
KR970003937A (en) Method of manufacturing metal oxide silicon field effect transistor
KR970067646A (en) Method of forming a contact hole in a semiconductor device
KR970013036A (en) Gate manufacturing method of semiconductor device
KR970052317A (en) Method for forming micro contact window of semiconductor device
KR960026568A (en) Device isolation insulating film manufacturing method of semiconductor device
KR970054086A (en) Manufacturing Method of Semiconductor Unit Device
KR950021400A (en) Field oxide film manufacturing method
KR950014972A (en) Manufacturing Method of Semiconductor Device

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20050802

Year of fee payment: 8

LAPS Lapse due to unpaid annual fee