KR970051422A - Multi-bit Test Circuit of Semiconductor Memory Device - Google Patents

Multi-bit Test Circuit of Semiconductor Memory Device Download PDF

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Publication number
KR970051422A
KR970051422A KR1019950055754A KR19950055754A KR970051422A KR 970051422 A KR970051422 A KR 970051422A KR 1019950055754 A KR1019950055754 A KR 1019950055754A KR 19950055754 A KR19950055754 A KR 19950055754A KR 970051422 A KR970051422 A KR 970051422A
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KR
South Korea
Prior art keywords
memory device
semiconductor memory
bit
lines
test circuit
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KR1019950055754A
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Korean (ko)
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KR0172413B1 (en
Inventor
이중화
한진만
서동일
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김광호
삼성전자 주식회사
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Priority to KR1019950055754A priority Critical patent/KR0172413B1/en
Publication of KR970051422A publication Critical patent/KR970051422A/en
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Publication of KR0172413B1 publication Critical patent/KR0172413B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/26—Accessing multiple arrays
    • G11C29/28—Dependent multiple arrays, e.g. multi-bit arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders

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  • Tests Of Electronic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

1.청구범위에 기재된 발명이 속하는 기술 분야1. Technical field to which the invention described in the claims belongs

본 발명은 반도체 메모리장치에 관한 것으로, 특히 한번의 테스트사이클동안 다수의 메모리셀들에 대한 불량여부를 고속으로 테스트하는 멀티비트 테스트회로 및 상기 멀티비트 테스트회로를 구비하는 반도체 메모리장치에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a multi-bit test circuit for testing a plurality of memory cells at a high speed for one test cycle and a semiconductor memory device having the multi-bit test circuit.

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

종래의 반도체 메모리장치에 있어서, 한개의 입출력라인쌍에 다수의 비트라인쌍 및 컬럼선택라인들이 접속되어 있다. 따라서 이러한 반도체 메모리장치에서 한번의 테스트사이클동안 데이타을 방지하면서 테스트할 수 있는 메모리셀의 갯수는 한정되어 있다. 그러므로 모든 메모리셀들을 테스트하는 데는 많은 시간이 소요된다. 따라서 상기와 같은 구조를 가진 메모리장치는 테스트에 많은 시간이 소요되므로 반도체 메모리장치의 생산성향상을 저해하는 요인으로 작용하게 된다. 이러한 테스트시간을 절감하여 생산성이 향상된 반도에 메모리장치의 멀티비트 테스트회로를 구현하는 것이 본 발명의 과제이다.In a conventional semiconductor memory device, a plurality of bit line pairs and column select lines are connected to one input / output line pair. Therefore, the number of memory cells that can be tested while preventing data during one test cycle in the semiconductor memory device is limited. Therefore, it takes a lot of time to test all the memory cells. Therefore, since the memory device having the above structure takes a lot of time to test, it acts as a factor that inhibits the productivity improvement of the semiconductor memory device. An object of the present invention is to implement a multi-bit test circuit of a memory device on a peninsula having improved productivity by reducing such test time.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

다수개의 워드라인과, 상기 워드라인과 연직방향으로 접속된 비트라인쌍과 센스앰프와 입출력라인쌍 및 컬럼선택라인과, 소정갯수씩의 비트라인쌍에 접속된 메모리셀들로 구성되는 다수개의 서브블럭과, 상기 서브블럭에 접속된 서브블럭 제어회로를 구비하는 반도체 메모리장치의 멀티비트 테스트회로에 있어서, 상기 서브블럭 제어회로가 복수개의 입출력라인쌍 및 복수개의 컬럼선택라인들중 하나를 선택적으로 머지드 데이타라인쌍에 연결시키는 다수개의 입출력 멀티플렉서와, 상기 다수개의 머지드데이타라인에서 전송되는 데이타중 하나를 선택하는 다수의 머지드 멀티플렉서와, 상기 복수개의 머지드 멀티플렉서의 출력을 논리비교하는 다수의 제1비교기와, 상기 다수의 제1비교기의 출력을 입력하여 2차로 논리비교하는 제2비교기를 구비함을 특징으로 하는 반도체 메모리장치의 멀티비트 테스트회로를 구현하므로써 상기 본 발명의 과제를 달성하게 된다.A plurality of sublines including a plurality of word lines, a pair of bit lines connected in a vertical direction to the word lines, a sense amplifier, an input / output line pair, a column selection line, and memory cells connected to a predetermined number of pairs of bit lines In a multi-bit test circuit of a semiconductor memory device having a block and a subblock control circuit connected to the subblock, the subblock control circuit selectively selects one of a plurality of input / output line pairs and a plurality of column selection lines. A plurality of input / output multiplexers connected to pairs of merged data lines, a plurality of merged multiplexers for selecting one of data transmitted from the plurality of merged data lines, and a plurality of logical comparisons of outputs of the plurality of merged multiplexers A first comparator of the second comparator and a second comparator for logically comparing the outputs of the plurality of first comparators The above object of the present invention can be achieved by implementing a multi-bit test circuit of a semiconductor memory device.

4. 발명의 중요한 용도4. Important uses of the invention

테스트시간의 절감에 따라 생산성이 향상된 반도체 메모리장치.Semiconductor memory device with improved productivity by reducing test time.

Description

반도체 메모리장치의 멀티비트 테스트회로Multi-bit Test Circuit of Semiconductor Memory Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제4도는 본 발명의 실시예에 따른 멀티비트 테스트과정을 보여주는 도면.4 is a diagram illustrating a multi-bit test process according to an embodiment of the present invention.

제5는 상기 제4도의 메모리셀 구성을 보여주는 도면.5 is a diagram illustrating a memory cell configuration of FIG.

제6도는 상기 제4도를 구성하는 서브블럭제어회로의 구성을 보여주는 도면.FIG. 6 is a diagram showing the configuration of a subblock control circuit of FIG.

제7도는 제6도를 구성하는 MIO NUX의 상세회로도.7 is a detailed circuit diagram of the MIO NUX constituting FIG.

제8도는 제6도를 구성하는 MUX CON의 상세회로도.8 is a detailed circuit diagram of the MUX CON constituting FIG.

제9도는 제6도를 구성하는 IO MUX의 상세회로도.9 is a detailed circuit diagram of the IO MUX constituting FIG.

Claims (2)

다수개의 워드라인과, 상기 워드라인과 연직방향으로 접속된 비트라인쌍과 센스앰프와 입출력라인쌍 및 컬럼선택라인과, 소정갯수씩의 비트라인쌍에 접속된 메모리셀들로 구성되는 다수개의 서브블럭과, 상기 서브블럭에 접속된 서브블럭 제어회로를 구비하는 반도체 메모리장치의 멀티비트 테스트회로에 있어서 상기 서브블럭 제어회로가 복수개의 입출력라인쌍 및 복수개의 컬럼 선택라인들중 하나를 선택적으로 머지드 데이타라인쌍에 연결시키는 다수개의 입출력 멀티플렉서와, 상기 다수개의 머지드 데이타라인에서 전송되는 데이타중 하나를 선택하는 다수의 머지드 멀티플렉서와, 상기 복수개의 머지드 멀티플렉서의 출력을 논리비교하는 다수의 제1비교기와, 상기 다수의 제1비교기의 출력을 입력하여 2차로 논리비교하는 제2비교기를 구비함을 특징으로 하는 반도체 메모리장치의 멀티비트 테스트회로.A plurality of sublines including a plurality of word lines, a pair of bit lines connected in a vertical direction to the word lines, a sense amplifier, an input / output line pair, a column selection line, and memory cells connected to a predetermined number of pairs of bit lines In a multi-bit test circuit of a semiconductor memory device having a block and a subblock control circuit connected to the subblock, the subblock control circuit selectively merges one of a plurality of input / output line pairs and a plurality of column select lines. A plurality of input / output multiplexers connected to the paired data line pairs, a plurality of merged multiplexers for selecting one of data transmitted from the plurality of merged data lines, and a plurality of logical comparisons for outputs of the plurality of merged multiplexers. Comprising a first comparator and a second comparator for performing a second logical comparison by inputting the outputs of the plurality of first comparators Multi-bit test circuit of a semiconductor memory device, characterized in that. 제1항에 있어서, 상기 멀티비트 테스트회로가 입출력 센스앰프를 더 구비함을 특징으로 하는 반도체 메모리장치의 멀티비트 테스트회로.The multi-bit test circuit of claim 1, wherein the multi-bit test circuit further includes an input / output sense amplifier. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950055754A 1995-12-23 1995-12-23 Multi-bit test circuit of semiconductor memory device KR0172413B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100567044B1 (en) * 1999-01-20 2006-04-04 주식회사 하이닉스반도체 Multi-low compression test apparatus for dynamic random access memory

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150077989A (en) 2013-12-30 2015-07-08 에스케이하이닉스 주식회사 Test circuit of samiconductor apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100567044B1 (en) * 1999-01-20 2006-04-04 주식회사 하이닉스반도체 Multi-low compression test apparatus for dynamic random access memory

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