KR0172413B1 - Multi-bit test circuit of semiconductor memory device - Google Patents

Abstract

1. Technical field to which the invention described in the claims belongs

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a multi-bit test circuit for testing a plurality of memory cells at a high speed for one test cycle and a semiconductor memory device having the multi-bit test circuit.

2. The technical problem to be solved by the invention

In a conventional semiconductor memory device, a plurality of bit line pairs and column select lines are connected to one input / output line pair. Therefore, the number of memory cells that can be tested while preventing data during one test cycle in the semiconductor memory device is limited. Therefore, it takes a lot of time to test all the memory cells. Therefore, since the memory device having the above structure takes a lot of time to test, it acts as a factor that inhibits the productivity improvement of the semiconductor memory device. An object of the present invention is to implement a multi-bit test circuit of a memory device on a peninsula having improved productivity by reducing such test time.

3. Summary of Solution to Invention

A plurality of sublines including a plurality of word lines, a pair of bit lines connected in a vertical direction to the word lines, a sense amplifier, an input / output line pair, a column selection line, and memory cells connected to a predetermined number of pairs of bit lines In a multi-bit test circuit of a semiconductor memory device having a block and a subblock control circuit connected to the subblock, the subblock control circuit selectively selects one of a plurality of input / output line pairs and a plurality of column selection lines. A plurality of input / output multiplexers connected to pairs of merged data lines, a plurality of merged multiplexers for selecting one of data transmitted from the plurality of merged data lines, and a plurality of logical comparisons of outputs of the plurality of merged multiplexers A first comparator of the second comparator and a second comparator for logically comparing the outputs of the plurality of first comparators The above object of the present invention can be achieved by implementing a multi-bit test circuit of a semiconductor memory device.

4. Important uses of the invention

Semiconductor memory device with improved productivity by reducing test time.

Description

Multi-bit Test Circuit of Semiconductor Memory Device

1 is a schematic block diagram showing an arrangement of a general semiconductor memory device.

2 is a diagram illustrating a multi-bit test process according to the prior art.

3 is a diagram illustrating a memory cell configuration of FIG. 2.

4 is a diagram illustrating a multi-bit test process according to an embodiment of the present invention.

5 is a diagram illustrating a memory cell configuration of FIG.

FIG. 6 is a diagram showing the configuration of a subblock control circuit of FIG.

7 is a detailed circuit diagram of the MIO NUX constituting FIG.

8 is a detailed circuit diagram of the MUX CON constituting FIG.

9 is a detailed circuit diagram of the IO MUX constituting FIG.

10 is a detailed circuit diagram of a CSLG constituting FIG.

11 is a detailed circuit diagram of a first comparator constituting FIG.

12 is a detailed circuit diagram of a second comparator constituting FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device including a multi-bit test circuit for fast-casting defects of a plurality of memory cells during one test cycle and the multi-bit test circuit.

1 is a schematic block diagram showing an arrangement of a general semiconductor memory device. As shown in FIG. 1, a memory cell array region of a general semiconductor memory device is divided into several memory banks 100, 200, 300, and 400. A column decoder and a low decoder are connected to the memory banks 100, 200, 300, and 400, respectively. A plurality of internal circuits (not shown) are organically connected between the memory bank and the memory bank. Is connected.

In the general semiconductor memory device as shown in FIG. 1, a plurality of memory chips are fabricated on a wafer, the memory chips on the wafer are separated, and a package process is performed. In such a semiconductor memory device, it is essential to test a defect of memory cells completed through a predetermined process. There are many types of tests. It is largely divided into a wafer state test and a package state test. Wafer test is used to find and repair or remove defective chips. In addition, the test of the package state is a test used to find a bad memory chip generated during the package process. The defective memory cells found in the test may be replaced with spare cells using a redundancy circuit, or removed if the defects are severe. However, as the degree of integration of a semiconductor memory device increases, the time and cost of testing the memory cells increases. An increase in time and cost caused by the test is a factor that hinders productivity improvement. In order to reduce the time required, most memory devices currently used have a parallel test method for testing a plurality of memory cells at a time during a test cycle. So-called multi-bit test.

2 is a view showing a multi-bit test process according to the prior art. For convenience of description, it is assumed that FIG. 2 is a configuration of the memory bank 100 constituting FIG.

Referring to FIG. 2, the memory bank 100 is divided into several memory blocks MBa-MBn. Input / output line pairs are disposed between the memory block constituting the memory bank 100 and the memory block. In FIG. 2, two pairs of input / output line pairs are arranged on the left and right sides of the memory block. On the right side of the drawing of the memory bank 100, a column decoder 101 for controlling selection of a column selection line connected to a pair of bit lines constituting the memory bank 100 is disposed. A plurality of row decoders 102a-102n for controlling the selection of the word lines constituting the memory bank 100 are disposed at the bottom of the figure of the memory bank 100. Input terminals of one input / output sense amplifiers 111 to 118 are connected to the input / output line pairs, respectively. Output terminals of the input / output sense amplifiers 111-118 are connected to input terminals of the plurality of first comparators 120a-120i in predetermined number units. The output terminals of the first comparators 120a-120i are connected to the input terminal of the second comparator 130 through the first data line pairs FD00-FD0i. The output terminal of the second comparator is connected to the second data line SDO.

FIG. 3 is a diagram illustrating a configuration of memory cells constituting FIG. 2.

As shown in FIG. 3, a memory cell is a memory cell of a dynamic random access memory composed of one transistor and one capacitor. The input / output line pairs and the bead line pairs are arranged in a perpendicular direction to each other. The pair of bit lines is connected in an interleaved manner, and the pair of bit lines are commonly connected to adjacent memory blocks. One bit high sense amplifier is connected between the pair of bit lines. The bit line sense amplifier is a configuration of a shared sense amplifier which is commonly connected to adjacent memory blocks.

Before performing the multi-bit test operation, all memory cells write data of the same logic level, for example, 'high' or 'low' data at high speed. A refresh clock is used to execute this high speed write operation. In this state, data of the memory cell in which the write operation is performed is read. The operation is as follows. That is, some of the low address signals are decoded to activate some of the memory blocks of FIG. Next, a predetermined word line is selected according to the output of the low decoder connected to the activated memory block. According to the word line selection, a predetermined voltage difference occurs between a pair of bit lines of a plurality of memory cells connected to the selected word line. So-called charge sharing between the charge stored in the capacitor of the memory cell and the charge stored in the parasitic capacitor of the bit line. The voltage difference between the bit lines is sensed, that is sensed, in the bit line sense amplifier constituting FIG. After the sensing operation of the bit line is completed, a predetermined column selection line is selected by the output of the column decoder 101. According to the selection of the column selection line, the data carried in the bit line pair is transferred to the input / output line pair. Data carried on the input / output line pairs is sensed once again in the input / output sense amplifiers. Thus, multi-bits are accessed in one cycle. The outputs of the input / output sense amplifiers are first compared with each logic level in the first comparators 120a through 120i. If any one of a plurality of data accessed at the same time is input to the first comparators 120a-120i, it implies that there is a bad memory cell. In this case, the outputs of the first comparators 120a-120i are transmitted to the second comparator 130 through the first data line pair FD0a-FD0i and are secondarily compared. If the outputs of the first comparators 120a-120i transmitted to the second comparator 130 are the same, it is designed to output 'high' and to output 'low'. Such first and second comparators can be easily implemented using an exclusive OR gate used in a logic circuit. Through this process, multiple memory cells are tested in parallel during one test cycle. That is, the multibit test operation is executed. This multi-bit test operation is repeatedly performed to test whether all memory cells are defective.

However, in the architecture of the memory device in a circuit as shown in FIGS. 2 and 3, a plurality of bit line pairs and column select lines are connected to a pair of input lines. Therefore, the number of memory cells that can be tested while preventing data collision during one test cycle in the semiconductor memory device is limited. Therefore, it takes a lot of time to test all the memory cells. Therefore, since the memory device having the above structure takes a lot of time to test, it acts as a factor that inhibits the productivity improvement of the semiconductor memory device.

Accordingly, an object of the present invention is to provide a semiconductor memory device for testing a larger number of memory cells in a multi-bit test operation.

Another object of the present invention is to provide a multi-bit test circuit of a semiconductor memory device for testing a large number of memory cells in one test cycle.

In order to achieve the object of the present invention, a plurality of word lines, a bit line pair connected in a vertical direction to the word line, a sense amplifier, an input / output line pair, a column selection line, and a predetermined number of bit line pairs are connected. The multi-bit test circuit of a semiconductor memory device according to the present invention includes a plurality of subblocks composed of memory cells and a subblock control circuit connected to the subblocks. A plurality of input / output multiplexers for selectively connecting one of a plurality of column select lines to a pair of merged data lines, a plurality of merged multiplexers for selecting one of data transmitted from the plurality of merged data lines, and the plurality of merges And a plurality of first comparators for comparing the outputs of the multiplexer and the outputs of the plurality of first comparators And a second comparator configured to logically compare a second input.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. Circuits and elements performing the same configuration and the same operation in the drawings will use the same reference numerals and the same reference numerals wherever possible.

4 is a diagram illustrating a multi-bit test process according to an exemplary embodiment of the present invention, and FIG. 5 is a diagram illustrating a memory cell configuration of FIG. 4. In FIG. 4, the memory bank 100 of FIG. 1 is assumed to be the same as in the related art.

Referring to FIG. 4, the memory bank 100 is divided into several memory blocks MBa-MBn in the vertical direction on the drawing. If the capacity of the memory device shown in FIG. 1 is 16 megabits and the memory blocks are divided into eight, the capacity of each memory block is 512 kilobits. Each of the memory blocks includes 512 bit line pairs and 1024 word lines. The memory bank 100 is divided into several subblocks SBa-SBk in the horizontal direction in the drawing, and 32 bit line pairs are connected to each subblock. Since the number of bit line pairs is assumed to be 512 pairs, the number of subblocks is 16. Unlike FIG. 4, the input / output line pairs are connected in parallel with the bit line pairs through the column select gate. This is as shown in FIG. Subblock control circuits 151a-151k are disposed on the right side of the memory bank 100 to control the selection of column selection lines connected to the pair of bit lines constituting the memory bank 100. Output terminals of the subblock control circuits are connected to output terminals of the first comparators 152a to 152k. Output terminals of the first comparators 152a to 152k are connected to an input terminal of the second comparator 160 through the first data line pair FD1-FDi. The output terminal of the second comparator is connected to the second data line pair SDO. A plurality of row decoders 102a-102n controlling the selection of word lines constituting the memory bank 100 are disposed at the bottom of the drawing of the memory bank 100.

As shown in FIG. 5, a memory cell is a memory cell of a dynamic random access memory composed of one transistor and one capacitor. As described above, the input / output line pairs are arranged parallel to each other in the horizontal direction. Therefore, one input / output line is connected to each bit line pair.

FIG. 6 is a diagram showing the configuration of the subblock control circuit of FIG. 4, FIG. 7 is a detailed circuit diagram of the MIO MUX of FIG. 6, and FIG. 8 is a detail of the MUX CON of FIG. 9 is a detailed circuit diagram of the IO MUX constituting FIG. 6, and FIG. 10 is a detailed circuit diagram of the CSLG constituting FIG. 11 and 12 are detailed circuit diagrams of the first comparator and the second comparator constituting FIG.

A multi-bit test operation of a semiconductor memory device according to an embodiment of the present invention will be described with reference to FIGS. 1 and 4 through 12. FIG.

In the configuration of FIG. 4, input / output line pairs are individually connected to one bit line pair. In normal mode operation, one or several input / output line pairs and column selection lines are enabled for each subblock, and one or several data are transmitted to the primary comparator through the subblock control circuit. The normal input / output operation is performed by selectively outputting one or several pieces of data from the first comparator. In the multi-bit test mode, the same data is written to all the memory cells as in the conventional case. The write operation can be performed at high speed by using the refresh cycle as in the prior art. Next, an operation of reading data stored in the memory cell is performed. The read operation is as follows. That is, as shown in FIG. 6, since the pair of bit lines is connected to the input / output mill multiplexer IO MUX in units of eight pairs, four input / output multiplexers IO MUX are connected to the subblock. Therefore, four data can be accessed in each subblock in one access operation. The operation of selecting a specific column selection line among four column selection lines in each of the subblocks is determined by the column address signal CAi input to the column selection line control circuit CSLG for controlling the input / output multiplexer. By operating four column selection lines at the same time for each subblock, as many data as (4 × subblocks) can be simultaneously loaded onto the merged data line pair (MIO) through the input / output line pairs. do. Assuming that the number of bit line pairs is 512, so that there are 16 subblocks, 64 bit memory cells can be tested simultaneously during one test cycle. The merged data line pair MIO performs a multiplexing operation in a merged multiplexer MIO MUX. The output of the merged multiplexer MIO MUX is sensed and amplified by input / output line sense amplifiers IO S / A. The output of the input / output line sense amplifier (IO S / A) compares four data in the first comparator existing for each subblock, and outputs a 'high' level if the result value is the same and the result value is different. If 'low' level is output. Here, the arrangement of the input / output line sense amplifiers IO S / A may be disposed between the input / output multiplexer IO MUX and the merged multiplexer MIO MUX, as necessary. The outputs of the first comparators again perform a comparison operation in the second comparator. Therefore, when any one of the accessed memory cells stores other data, the 'low' level is output, so that it can be detected and replaced by using a redundancy circuit.

As many input / output line pairs exist as described above, the comparator as shown in FIGS. 11 and 12 performs the comparison operation. In normal operation, one data is transmitted. In multi-bit test operation, the logic level of all data is compared and the result value is output.

For reference, the function of the subblock control circuit in FIG. 6 will be briefly described as follows. That is, the predetermined column selection line is selected using a circuit as shown in FIG. Further, as shown in FIG. 7, the multiplexer is multiplexed in the IO multiplexer, which is composed of a certain number of input / output line pairs and column selection lines. In addition, as shown in FIG. 4, the input / output multiplexer IO MUX is used to transfer the data of the input / output line pair and the column selection line to the merged data line. In addition, by composing a merged data line pair that is an output of a plurality of data input / output multiplexers, the output is transferred to the next comparators. Such a subblock control circuit is configured as shown in FIG. 4, and an additional circuit configuration is also shown when one column redundancy is provided for each subblock, and a shared column redundancy that can be repaired by two subblocks is shown.

In the memory device employing this structure, multiple column select lines of a plurality of subblocks can be operated in a plurality of blocks during a multi-bit test operation, thereby enabling testing of many bits of memory cells at one time. Therefore, when the semiconductor memory device according to the present invention is implemented, it is possible to save time due to the test, which further improves the productivity of the semiconductor memory device.

Claims (2)

A plurality of subblocks comprising a plurality of word lines, a pair of bit lines connected in a vertical direction to the word lines, a sense amplifier, an input / output line pair, a column selection line, and memory cells connected to a predetermined number of pairs of bit lines. And, in the multi-bit test circuit of the semiconductor memory device having a subblock control circuit connected to the subblock, the subblock control circuit selectively merges one of a plurality of input / output line pairs and a plurality of column select lines. A plurality of input / output multiplexers connected to pairs of data lines, a plurality of merged multiplexers for selecting one of data transmitted from the plurality of merged data lines, and a plurality of products for logically comparing the outputs of the plurality of merged multiplexers. Comparing a first comparator, and a second comparator to input the output of the plurality of first comparators and logically compare the second A multi-bit test circuit for a semiconductor memory device. The multi-bit test circuit of claim 1, wherein the multi-bit test circuit further includes an input / output sense amplifier.