KR970067378A

KR970067378A - Synchronous semiconductor memory device

Info

Publication number: KR970067378A
Application number: KR1019960007216A
Authority: KR
Inventors: 서동일; 정세진
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1996-03-18
Filing date: 1996-03-18
Publication date: 1997-10-13
Also published as: KR100221073B1

Abstract

1. 청구 범위에 기재된 발명이 속한 기술분야1. Technical field to which the invention described in the claims belongs

동기식 반도체 메모리 장치에 관한 것이다.To a synchronous semiconductor memory device.

2. 발명이 해결하려고 하는 기술적 과제2. Technical Challenges to be Solved by the Invention

데이타간의 스큐와 테스트 시간을 감소시킬 수 있는 동기식 반도체 메모리장치의 병렬 비트라인 테스트회로 및 그 방법을 제공함에 있다.A parallel bit line test circuit of a synchronous semiconductor memory device capable of reducing skew between data and a test time, and a method therefor.

3. 발명의 해결방법의 요지3. The point of the solution of the invention

공유 데이타라인에 출력단이 각기 연결된 다수의 입출력 데이타 센스앰프와, 상기 입출력 데이타 센스앰프와 연결되며 행과 열의 매트릭스로 이루어진 복수개의 메모리 셀들을 가지는 다수의 메모리 뱅크들을 동일 칩상에 가지며, 외부 클럭에 동기되어 동작하는 동기식 반도체 메모리 장치에서 상기 메모리 셀들과 각기 연결된 비트라인들을 통하여 상기 메모리 셀들의 결함을 테스트하는 병렬 비트라인 테스트회로는 상기 다수개의 입출력 센스앰프의 출력단에 접속되며 상기 메모리 셀들에 미리 설정된 레벨로 기입한 소정 데이타를 비교하여 상기 동기식 반도체 메모리 장치의 출력패드로 전송시키는 비교수단으로 구성됨을 특징으로 한다.A plurality of memory banks each having a plurality of memory cells connected to the input and output data sense amplifiers and having a matrix of rows and columns on the same chip, A parallel bit line test circuit for testing a defect of the memory cells through bit lines connected to the memory cells in a synchronous semiconductor memory device operating at a predetermined level is connected to an output terminal of the plurality of input and output sense amplifiers, And comparing means for comparing the predetermined data written in the register with the output pad of the synchronous semiconductor memory device.

4. 발명의 중요한 용도4. Important Uses of the Invention

고속의 동기식 반도체 메모리 장치에 적합하게 사용된다.And is suitably used for a high-speed synchronous semiconductor memory device.

Description

Synchronous semiconductor memory device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제2도는 본 발명에 따라 구성된 동기식 반도체 메모리 장치의 개략적인 블럭도, 제3도는 본 발명의 실시예에 따라 병렬 비트라인 테스트를 하기 위한 구체 회로도.FIG. 2 is a schematic block diagram of a synchronous semiconductor memory device constructed in accordance with the present invention; FIG. 3 is a specific circuit diagram for a parallel bit line test according to an embodiment of the present invention; FIG.

Claims

A plurality of memory banks each having a plurality of memory cells connected to the input and output data sense amplifiers and having a matrix of rows and columns on the same chip, A parallel bit line test circuit for testing defects in the memory cells through bit lines connected to the memory cells in a synchronous semiconductor memory device, the parallel bit line test circuit being connected to the output terminals of the plurality of input / output sense amplifiers, And comparing means for comparing the predetermined data written at the set level to the output pad of the synchronous semiconductor memory device.

2. The parallel bit line test circuit of claim 1, wherein the comparing means comprises four logic gates per bank of the banks.

3. The parallel bit line test circuit of claim 2, wherein the logic gate is a NAND gate having four input terminals.

4. The parallel bit line test circuit of claim 3, wherein the logic gate is a Noah gate having four input terminals.

A plurality of memory banks each having a plurality of memory cells connected to the input and output data sense amplifiers and having a matrix of rows and columns on the same chip, Wherein the connection of the shared data lines commonly connected to the outputs of the input and output sense amplifiers between the banks is performed such that the output pad allocation between the banks is different from the output of the other input / And the data lines are equally allocated with the lengths of the data lines to perform a write operation and a read operation.

A plurality of memory banks each having a plurality of memory cells connected to the input and output data sense amplifiers and having a matrix of rows and columns on the same chip, A method for testing a defect in a memory cell through a plurality of bit lines connected to the memory cells in a synchronous semiconductor memory device, the method comprising the steps of: Lt; RTI ID = 0.0 > 1, < / RTI >

7. The method of claim 6, wherein the test step is a package step.

7. The method of claim 6, wherein the testing step comprises testing in a wafer state.

※ Note: It is disclosed by the contents of the first application.