KR970049005A - Method of forming fine contact pattern of semiconductor device - Google Patents
Method of forming fine contact pattern of semiconductor device Download PDFInfo
- Publication number
- KR970049005A KR970049005A KR1019950059295A KR19950059295A KR970049005A KR 970049005 A KR970049005 A KR 970049005A KR 1019950059295 A KR1019950059295 A KR 1019950059295A KR 19950059295 A KR19950059295 A KR 19950059295A KR 970049005 A KR970049005 A KR 970049005A
- Authority
- KR
- South Korea
- Prior art keywords
- region
- forming
- semiconductor device
- photoresist pattern
- fine contact
- Prior art date
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Abstract
본 발명은 더미 콘택 패턴을 이용하여 반도체 장치의 미세 콘택홀을 형성하기 위하여 포토레지스트 패턴을 열플로우시키는 공정에서 상기 포토레지스트 패턴이 휘어지는 것을 방지할 수 있는 반도체 장치의 미세 콘택 패턴 형성 방법에 관한 것으로, 소자분리 영역을 형성하여 활성영역4과 비활성영역이 정의되어 있되, 그 위에 비트라인을 갖는 층간절연막을 구비한 반도체 장치의 미세 콘택 패턴 형성 방법에 있어서, 상기 층간절연막상에 포토레지스트 패턴을 형성하여 메모리 셀 영역의 콘택홀이 형성될 영역을 정의하되, 상기 메모리 셀 영역과 주변영역의 경계상에 더미 포토레지스트 패턴을 형성하는 공정을 포함하고 있다. 이와같은 방법에 의해서, 반도체 장치의 미세 콘택홀을 형성하는 공정에서 마스크로 사용되는 포토레지스트 패턴을 열플로우시키는 공정에서 상기 포토레지스트 패턴이 휘어지는 것을 방지할 수 있다.The present invention relates to a method of forming a fine contact pattern of a semiconductor device capable of preventing the photoresist pattern from bending in a process of thermally flowing a photoresist pattern to form a fine contact hole of a semiconductor device using a dummy contact pattern. And forming a device isolation region to define an active region 4 and an inactive region, and forming a fine contact pattern of a semiconductor device having an interlayer insulating layer having a bit line thereon, wherein a photoresist pattern is formed on the interlayer insulating layer. And defining a region in which a contact hole of the memory cell region is to be formed, and forming a dummy photoresist pattern on a boundary between the memory cell region and a peripheral region. By such a method, it is possible to prevent the photoresist pattern from bending in a process of thermally flowing a photoresist pattern used as a mask in a process of forming a fine contact hole of a semiconductor device.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제2A도 내지 제2B도는 본 발명의 실시예에 따른 반도체 장치의 미세 콘택 패턴을 보여주고 있는 평면도 및 단면도.2A to 2B are plan and cross-sectional views showing a fine contact pattern of a semiconductor device according to an embodiment of the present invention.
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950059295A KR970049005A (en) | 1995-12-27 | 1995-12-27 | Method of forming fine contact pattern of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950059295A KR970049005A (en) | 1995-12-27 | 1995-12-27 | Method of forming fine contact pattern of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
KR970049005A true KR970049005A (en) | 1997-07-29 |
Family
ID=66620022
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950059295A KR970049005A (en) | 1995-12-27 | 1995-12-27 | Method of forming fine contact pattern of semiconductor device |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR970049005A (en) |
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1995
- 1995-12-27 KR KR1019950059295A patent/KR970049005A/en not_active Application Discontinuation
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