KR970030582A - How to Form a Via Resistance Check Pattern - Google Patents

How to Form a Via Resistance Check Pattern Download PDF

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Publication number
KR970030582A
KR970030582A KR1019950045676A KR19950045676A KR970030582A KR 970030582 A KR970030582 A KR 970030582A KR 1019950045676 A KR1019950045676 A KR 1019950045676A KR 19950045676 A KR19950045676 A KR 19950045676A KR 970030582 A KR970030582 A KR 970030582A
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KR
South Korea
Prior art keywords
metal
via resistance
forming
polysilicon
check pattern
Prior art date
Application number
KR1019950045676A
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Korean (ko)
Other versions
KR100192578B1 (en
Inventor
김만준
Original Assignee
김광호
삼성전자 주식회사
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Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950045676A priority Critical patent/KR100192578B1/en
Publication of KR970030582A publication Critical patent/KR970030582A/en
Application granted granted Critical
Publication of KR100192578B1 publication Critical patent/KR100192578B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

1. 청구범위에 기재된 발명이 속하는 기술 분야; 비아 저항의 정확한 체크 동작을 수행하기 위한 비아 저항 체크 패턴 형성방법에 관한 것이다.1. the technical field to which the invention described in the claims belongs; A method of forming a via resistance check pattern for performing an accurate check operation of a via resistance is disclosed.

2. 발명이 해결하려고 하는 기술적 과제; 비아 저항의 정확한 체크 동작을 수행하는 비아 저항 체크 패턴 형성 방법을 제공함에 있다.2. The technical problem to be solved by the invention; The present invention provides a method of forming a via resistance check pattern for performing an accurate check operation of a via resistance.

3. 발명의 해결방법의 요지; 기판 상에 차례로 형성된 국부산화막 및 폴리실리콘과, 상기 폴리실리콘상에 형성된 층간절연막내에 각기 이격되어 형성된 제1메탈과, 상기 제1메탈 상부에 차례로 형성될 제 2메탈과의 콘택을 이루기 위한 각기 폴리실리콘 메탈의 비아 홀의 사이즈를 최소한의 디자인 룰을 기준으로 각기 차별화시키는 것을 요지로 한다.3. Summary of the Solution of the Invention; Each poly for forming contact between a local oxide film and a polysilicon formed on the substrate in turn, a first metal formed spaced apart from each other in the interlayer insulating film formed on the polysilicon, and a second metal to be sequentially formed on the first metal; The point is to differentiate the size of the via hole of silicon metal based on the minimum design rule.

4. 발명의 중요한 용도; 비아 저항 체크 패턴 형성 방법에 적합하다.4. Significant use of the invention; It is suitable for the method of forming the via resistance check pattern.

Description

비아 저항 체크 패턴 형성 방법How to Form a Via Resistance Check Pattern

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명의 일실시예에 따른 TEG내의 비아저항을 체크하기 위한 패턴을 보인 도면.2 is a diagram showing a pattern for checking via resistance in a TEG according to an embodiment of the present invention.

Claims (3)

반도체 제조공정에서의 비아 저항의 정확한 체크 동작을 수행하기 위한 비아 저항 체크 패턴 형성 방법에 있어서; 기판 상에 차례로 형성된 국부산화막 및 폴리실리콘과, 상기 폴리실리콘 상에 형성된 층간절연막내에 각기 이격되어 형성된 제1,2메탈과, 상기 제 2메탈 상부에 차례로 형성될 제3메탈과의 콘택을 이루기 위한 폴리실리콘 메탈의 비아 홀이 단차로서 이루어지는 것을 특징으로 하는 비아 저항 체크 패턴 형성 방법.A method of forming a via resistance check pattern for performing an accurate check operation of a via resistance in a semiconductor manufacturing process; For forming a contact between a local oxide film and polysilicon formed sequentially on a substrate, first and second metals spaced apart from each other in an interlayer insulating film formed on the polysilicon, and a third metal to be sequentially formed on the second metal; A via resistance check pattern forming method comprising via holes of polysilicon metal as steps. 반도체 제조공정에서의 비아 저항의 정확한 체크 동작을 수행하기 위한 비아 저항 체크 패턴 형성 방법에 있어서; 기판 상에 차례로 형성된 국부산화막 및 폴리실리콘과, 상기 폴리실리콘 상에 형성된 층간절연막내에 각기 이격되어 형성된 제1,2메탈과, 상기 제2 메탈 상부에 차례로 형성될 제 3메탈과의 콘택을 이루기 위한 각기 폴리실리콘 메탈의 비아 홀과 비아 홀 사이의 길이를 차별화시키는 것을 특징으로 하는 비아 저항 체크 패턴 형성 방법.A method of forming a via resistance check pattern for performing an accurate check operation of a via resistance in a semiconductor manufacturing process; For forming a contact between a local oxide film and polysilicon formed on a substrate in turn, first and second metals spaced apart from each other in an interlayer insulating film formed on the polysilicon, and a third metal to be sequentially formed on the second metal. A method of forming a via resistance check pattern, characterized in that differentiating the length between via holes and via holes of polysilicon metal, respectively. 반도체 제조공정에서의 비아 저항의 정확한 체크 동작을 수행하기 위한 비아 저항 체크 패턴 형성 방법에 있어서; 기판 상에 차례로 형성된 국부산화막 및 폴리실리콘과, 상기 폴리실리콘 상에 형성된 층간절연막내에 각기 이격되어 형성된 제1 메탈과, 상기 제 1메탈 상부에 차례로 형성될 제 2메탈과의 콘택을 이루기 위한 각기 폴리실리콘 메탈의 비아 홀의 사이즈를 최소한의 디자인 룰을 기준으로 각기 차별화 시키는 것을 특징으로 하는 비아 저항 체크패턴 방법.A method of forming a via resistance check pattern for performing an accurate check operation of a via resistance in a semiconductor manufacturing process; Local poly-oxides and polysilicon formed sequentially on the substrate, a first metal formed to be spaced apart in the interlayer insulating film formed on the polysilicon and each of the poly for making contact with the second metal to be formed on the first metal in turn Via resistance check pattern method characterized by differentiating the size of the via hole of the silicon metal based on the minimum design rule. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950045676A 1995-11-30 1995-11-30 Pattern forming method for checking via resistance KR100192578B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950045676A KR100192578B1 (en) 1995-11-30 1995-11-30 Pattern forming method for checking via resistance

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950045676A KR100192578B1 (en) 1995-11-30 1995-11-30 Pattern forming method for checking via resistance

Publications (2)

Publication Number Publication Date
KR970030582A true KR970030582A (en) 1997-06-26
KR100192578B1 KR100192578B1 (en) 1999-06-15

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KR1019950045676A KR100192578B1 (en) 1995-11-30 1995-11-30 Pattern forming method for checking via resistance

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