KR970030372A - 반도체 장치 제조방법 - Google Patents

반도체 장치 제조방법 Download PDF

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Publication number
KR970030372A
KR970030372A KR1019960055236A KR19960055236A KR970030372A KR 970030372 A KR970030372 A KR 970030372A KR 1019960055236 A KR1019960055236 A KR 1019960055236A KR 19960055236 A KR19960055236 A KR 19960055236A KR 970030372 A KR970030372 A KR 970030372A
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South Korea
Prior art keywords
film
gate electrode
forming
side wall
drain region
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KR1019960055236A
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KR100233221B1 (ko
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코찌 토리이
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가네꼬 히사시
닛폰 덴키주식회사
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Publication of KR970030372A publication Critical patent/KR970030372A/ko
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Publication of KR100233221B1 publication Critical patent/KR100233221B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

티타늄 막과 폴리실리콘 막은 실기사이드 TiSi2막을 만들기 위해 상호 작용하도록 되어진다. 그 후에, 측면벽(side wall)의 윗부분 끝은 전도성 TiSix 막을 전기적으로 제거시키기 위해, 폴리시 오프(polish off) 되어진다. 상기 전도성 Tisix 막은 실리사이드가 형성될 때 측면벽의 윗부분 끝에 형성된다. 그러므로 게이트 전극과 소스-드레인 영역위에 있는 실리사이드막의 막저항(layer resistance)을 낮게 유지하는 것과 소스-드레인 영역과 게이트전극이 단락(short-circuit)되는 방지하는 것이 가능하다.

Description

반도체 장치 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
1(a) 내지 1(e)는 종래의 셀프 얼라인드 실리사이드 과정(self-aligned silicide process)에 따라 0.35μm의 크기를 가진 N-채널 MOSFET을 제조하는 방법을 부분적으로 도시한 단면도.

Claims (4)

  1. 반도체 기판위에 게이트 전극과 소스-드레인 영역을 갖는 반도체 장치를 제조하는 방법에 있어서 상기 제조방법은, 반도체 기판 위에 게이트 산화막과 게이트 전극을 형성시키는 단계와, 게이트 전극의 측면에 측면벽(side wall)을 형성시키는 단계와, 게이트 전극과 측면벽을 마스크(mask)로 사용하면서, 셀프-얼라인드 소스-드레인 영역을 형성하는 단계와, 반도체 기판의 전체 표면위에 내화금속막을 형성시키는 단계와, 내화금속막과 실리콘이 서로 반응하도록 하여 실리사이드를 만드는 단계와, 실리콘과 반응하지 않았던 내화금속막의 한 부분을 제거하는 단계와, 측면벽의 윗부분 끝을 폴리싱 오프(polishing off)하는 단계로 구성되어 있는 방법.
  2. 제1항에 있어서, 상기 측면벽은 실리콘 막으로 구성되어 있는 반도체 장치 제조방법.
  3. 반도체 기판위에 게이트 전극과 소스-드레인 영역을 갖는 반도체 장치를 제조하는 방법에 있어서 상기 제조 방법은, 반도체 기관 위에 게이트 산화막과 게이트 전극을 형성시키는 단계와, 게이트 전극의 측면에 측면벽(side wall)을 형성시키는 단계와, 게이트 전극과 측면벽을 마스크(mask)로 사용하면서, 셀프-얼라인드 소스-드레인 영역을 형성하는 단계와, 반도체 기판의 전체 표면위에 내화금속막을 형성시키는 단계와, 내화금속막과 실리콘이 서로 반응하도록 하여 실리사이드를 만드는 단계와, 측면벽의 윗부분 끝을 폴리싱 오프(polishing off)하는 단계와, 실리콘과 반응하지 않았던 내화금속막의 한 부분을 제거하는 단계로 구성되어 있는 방법.
  4. 제3항에 있어서, 상기 측면벽은 실리콘막으로 구성되어 있는 방법.
KR1019960055236A 1995-11-20 1996-11-19 반도체 장치 제조 방법 KR100233221B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP95-301650 1995-11-20
JP7301650A JP2785772B2 (ja) 1995-11-20 1995-11-20 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
KR970030372A true KR970030372A (ko) 1997-06-26
KR100233221B1 KR100233221B1 (ko) 1999-12-01

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US (1) US5693550A (ko)
JP (1) JP2785772B2 (ko)
KR (1) KR100233221B1 (ko)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5843834A (en) * 1996-08-08 1998-12-01 National Semiconductor Corporation Self-aligned POCL3 process flow for submicron microelectronics applications using amorphized polysilicon
JPH11135745A (ja) * 1997-10-29 1999-05-21 Toshiba Corp 半導体装置及びその製造方法
US5923986A (en) * 1998-09-17 1999-07-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a wide upper top spacer to prevent salicide bridge
TW454251B (en) * 1998-11-30 2001-09-11 Winbond Electronics Corp Diode structure used in silicide process
US6417098B1 (en) * 1999-12-09 2002-07-09 Intel Corporation Enhanced surface modification of low K carbon-doped oxide
US6534388B1 (en) * 2000-09-27 2003-03-18 Chartered Semiconductor Manufacturing Ltd. Method to reduce variation in LDD series resistance
CN100442541C (zh) * 2001-03-23 2008-12-10 华邦电子股份有限公司 适用于自动对准金属硅化物工艺的半导体元件
JP2003253482A (ja) * 2002-03-01 2003-09-10 Ngk Insulators Ltd チタン系膜及びチタン酸化物の除去方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5286678A (en) * 1991-10-31 1994-02-15 Intel Corporation Single step salicidation process
TW209308B (en) * 1992-03-02 1993-07-11 Digital Equipment Corp Self-aligned cobalt silicide on MOS integrated circuits
JPH07183518A (ja) * 1993-11-15 1995-07-21 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
KR0135163B1 (ko) * 1993-12-16 1998-04-22 문정환 얕은 접합의 소오스/드레인영역과 실리사이드를 갖는 모스트랜지스터의 제조방법
US5472894A (en) * 1994-08-23 1995-12-05 United Microelectronics Corp. Method of fabricating lightly doped drain transistor device
US5491099A (en) * 1994-08-29 1996-02-13 United Microelectronics Corporation Method of making silicided LDD with recess in semiconductor substrate
US5576227A (en) * 1994-11-02 1996-11-19 United Microelectronics Corp. Process for fabricating a recessed gate MOS device
US5472897A (en) * 1995-01-10 1995-12-05 United Microelectronics Corp. Method for fabricating MOS device with reduced anti-punchthrough region
US5508212A (en) * 1995-04-27 1996-04-16 Taiwan Semiconductor Manufacturing Co. Salicide process for a MOS semiconductor device using nitrogen implant of titanium

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Publication number Publication date
JP2785772B2 (ja) 1998-08-13
US5693550A (en) 1997-12-02
KR100233221B1 (ko) 1999-12-01
JPH09148565A (ja) 1997-06-06

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