KR970029042A - Microcontroller with Error Monitoring Circuit - Google Patents

Microcontroller with Error Monitoring Circuit Download PDF

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Publication number
KR970029042A
KR970029042A KR1019950045666A KR19950045666A KR970029042A KR 970029042 A KR970029042 A KR 970029042A KR 1019950045666 A KR1019950045666 A KR 1019950045666A KR 19950045666 A KR19950045666 A KR 19950045666A KR 970029042 A KR970029042 A KR 970029042A
Authority
KR
South Korea
Prior art keywords
microcontroller
address bus
processing unit
central processing
error
Prior art date
Application number
KR1019950045666A
Other languages
Korean (ko)
Other versions
KR0177741B1 (en
Inventor
김태찬
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950045666A priority Critical patent/KR0177741B1/en
Publication of KR970029042A publication Critical patent/KR970029042A/en
Application granted granted Critical
Publication of KR0177741B1 publication Critical patent/KR0177741B1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Microcomputers (AREA)

Abstract

1. 청구 범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION

마이크로 콘트롤러Microcontroller

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

간단한 구성을 가지는 마이크로 콘트롤러의 감시회로를 제공함에 있다.The present invention provides a supervisory circuit for a microcontroller having a simple configuration.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

중앙처리장치 100 및 어드레스 버스를 통해 상기 중앙처리장치 100와 연결된 내부 롬 200을 구비한 개선된 마이크로 콘트롤러는 상기 어드레스 버스에 연결되며 상기 어드레스 버스로 인가되는 롬 어드레스의 프로그램 카운터 값을 체크하여 오류 감지시 리셋신호 또는 인터럽트 신호를 발생하는 오류 감시수단을 내부에 가짐을 특징으로 한다.An improved microcontroller having an internal ROM 200 connected to the central processing unit 100 and to the central processing unit 100 via an address bus detects an error by checking a program counter value of a ROM address connected to the address bus and applied to the address bus. Error monitoring means for generating a reset signal or an interrupt signal at the time.

4. 발명의 중요한 용도4. Important uses of the invention

마이크로 콘트롤러의 감시회로로 사용한다.Used as a supervisory circuit of a microcontroller.

Description

오류 감시회로를 가지는 마이크로 콘트롤러Microcontroller with Error Monitoring Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 종래의 마이크로 콘트롤러의 내부 블럭도,1 is an internal block diagram of a conventional microcontroller,

제2도는 본 발명에 따른 마이크로 콘트롤러의 내부 블럭도,2 is an internal block diagram of a microcontroller according to the present invention;

제3도는 제2도중 오류 감시회로 300의 세부 회로도이다.3 is a detailed circuit diagram of the error monitoring circuit 300 in FIG.

Claims (3)

중앙처리장치 100 및 어드레스 버스를 통해 상기 중앙처리장치 100와 연결된 내부 롬 200을 구비한 마이크로 콘트롤러에 있어서; 상기 어드레스 버스에 연결되며 상기 어드레스 버스로 인가되는 롬 어드레스의 프로그램 카운터 값을 체크하여 오류 감지시 리셋신호 또는 인터럽트 신호를 발생하는 오류 감시수단을 내부에 가짐을 특징으로 하는 마이크로 콘트롤러.10. A microcontroller having an internal ROM 200 connected to the central processing unit 100 via a central processing unit 100 and an address bus; And an error monitoring means connected to the address bus and configured to generate a reset signal or an interrupt signal when an error is detected by checking a program counter value of a ROM address applied to the address bus. 제1항에 있어서, 상기 오류 감시수단은 프로그램 카운터 값을 디코딩하는 디코더 및 래치소자를 포함하는 것을 특징으로 하는 마이크로 콘트롤러.2. The microcontroller according to claim 1, wherein said error monitoring means includes a decoder and a latch element for decoding a program counter value. 중앙처리장치 100 및 어드레스 버스를 통해 상기 중앙처리장치 100와 연결된 롬 200을 구비한 마이크로 프로세서에 있어서 : 상기 어드레스 버스에 연결되고 상기 어드레스 버스로 인가되는 롬 어드레스의 프로그램 카운터 값을 미리 설정된 값과 비교하여 에러시 리셋신호 또는 인터럽트 신호를 발생하며 상기 중앙처리장치 100의 인터럽트 응답신호에 대응하여 상기 리셋신호를 클리어하는 감시수단을 가짐을 특징으로 하는 마이크로 프로세서.A microprocessor having a central processing unit 100 and a ROM 200 connected to the central processing unit 100 via an address bus, comprising: comparing a program counter value of a ROM address connected to the address bus and applied to the address bus with a preset value; And a monitoring means for generating a reset signal or an interrupt signal in case of an error and clearing the reset signal in response to an interrupt response signal of the central processing unit 100. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950045666A 1995-11-30 1995-11-30 Microcontroller having error detection circuit KR0177741B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950045666A KR0177741B1 (en) 1995-11-30 1995-11-30 Microcontroller having error detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950045666A KR0177741B1 (en) 1995-11-30 1995-11-30 Microcontroller having error detection circuit

Publications (2)

Publication Number Publication Date
KR970029042A true KR970029042A (en) 1997-06-26
KR0177741B1 KR0177741B1 (en) 1999-05-15

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950045666A KR0177741B1 (en) 1995-11-30 1995-11-30 Microcontroller having error detection circuit

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KR (1) KR0177741B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100316520B1 (en) * 1998-12-30 2002-02-19 김영환 Microcontroller with Malfunction Protection

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KR0177741B1 (en) 1999-05-15

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