KR930023807A - Watchdog Timing Circuit - Google Patents

Watchdog Timing Circuit Download PDF

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Publication number
KR930023807A
KR930023807A KR1019920009197A KR920009197A KR930023807A KR 930023807 A KR930023807 A KR 930023807A KR 1019920009197 A KR1019920009197 A KR 1019920009197A KR 920009197 A KR920009197 A KR 920009197A KR 930023807 A KR930023807 A KR 930023807A
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KR
South Korea
Prior art keywords
output
processing unit
central processing
latch
signal
Prior art date
Application number
KR1019920009197A
Other languages
Korean (ko)
Other versions
KR940008853B1 (en
Inventor
김덕수
Original Assignee
정용문
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 정용문, 삼성전자 주식회사 filed Critical 정용문
Priority to KR1019920009197A priority Critical patent/KR940008853B1/en
Publication of KR930023807A publication Critical patent/KR930023807A/en
Application granted granted Critical
Publication of KR940008853B1 publication Critical patent/KR940008853B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/14—Time supervision arrangements, e.g. real time clock

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)

Abstract

중앙처리장치(10)를 구비한 시스템의 리세트 회로에 있어서, 상기 중앙처리장치(10)의 출력에 의해 워치독 타이밍의 정지/동작을 지시하고 워치독 타이밍을 위한 상기 중앙처리장치(10)의 출력을 래치하여 상기 중앙처리장치(10)의 초기화 신호와 상기 래치(20)의 클리어 신호에 의해 워치독 주기를 결정한다.A reset circuit of a system having a central processing unit (10), wherein the output of the central processing unit (10) instructs stop / operation of the watchdog timing and the central processing unit (10) for watchdog timing. The watchdog cycle is determined by latching the output of the signal by the initialization signal of the CPU 10 and the clear signal of the latch 20.

상기 주기결정 출력을 클리어신호로 하여 클럭단(CLK)의 신호를 카운팅하고 상기 카운팅 값과 래치(30)의 출력을 비교하여 상기 중앙처리장치(10)를 리세트시키기 위한 리셋신호를 발생하도록 되어 있다.The clock signal CLK is counted using the period determination output as a clear signal, and the reset signal for resetting the CPU 10 is generated by comparing the counting value with the output of the latch 30. have.

Description

워치독 타이밍회로Watchdog Timing Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 회로도.2 is a circuit diagram according to the present invention.

Claims (1)

중앙처리장치(10)를 구비한 시스템의 리세트 회로에 있어서, 상기 중앙처리장치(10)의 출력에 의해 워치독 타이밍의 정지/동작을 지시하는 제1 래치(20)와, 워치독 타이밍을 위한 상기 중앙처리장치(10)의 출력을 래치하는 제3 래치(30)와, 상기 중앙처리장치(10)의 초기화 신호와 제1 래치(20)의 클리어 신호에 의해 워치독 주기를 결정하는 노아게이트(40)와, 상기 노아게이트(40)의 출력을 클리어신호로 하여 클럭단(CLK)의 신호를 카운팅하는 카운터(50)와, 상기 카운터(50)와 제3 래치(30)의 출력을 비교하는 비교기(60)와, 상기 중앙처리장치(10)를 리세트시키기 위한 리셋회로(90)와, 상기 클럭단(CLK)의 클럭을 인버터(70)에서 반전한 클럭으로 상기 비교기(60)의 출력을 래치하여 상기 리셋회로(90)의 리셋아웃 신호를 발생하는 제2 래치회로(80)로 구성됨을 특징으로 하는 워치독 타이밍 회로.A reset circuit of a system having a central processing unit (10), the first latch (20) instructing the stop / operation of the watchdog timing by the output of the central processing unit (10), and the watchdog timing. Noah for determining the watchdog period by the third latch 30 for latching the output of the central processing unit 10 and the initialization signal of the central processing unit 10 and the clear signal of the first latch 20. A counter 50 for counting a signal at the clock stage CLK with the gate 40 and the output of the noble gate 40 as a clear signal, and an output of the counter 50 and the third latch 30. The comparator 60 to be compared, the reset circuit 90 for resetting the central processing unit 10, and the clock of the clock stage CLK with the clock inverted by the inverter 70. And a second latch circuit 80 for latching the output of the reset circuit 90 to generate the reset out signal of the reset circuit 90. Watchdog timing circuitry. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920009197A 1992-05-28 1992-05-28 Watch-dog timing circuit KR940008853B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920009197A KR940008853B1 (en) 1992-05-28 1992-05-28 Watch-dog timing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920009197A KR940008853B1 (en) 1992-05-28 1992-05-28 Watch-dog timing circuit

Publications (2)

Publication Number Publication Date
KR930023807A true KR930023807A (en) 1993-12-21
KR940008853B1 KR940008853B1 (en) 1994-09-28

Family

ID=19333793

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920009197A KR940008853B1 (en) 1992-05-28 1992-05-28 Watch-dog timing circuit

Country Status (1)

Country Link
KR (1) KR940008853B1 (en)

Also Published As

Publication number Publication date
KR940008853B1 (en) 1994-09-28

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