KR970055453A - Watchdog timer - Google Patents

Watchdog timer Download PDF

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Publication number
KR970055453A
KR970055453A KR1019950057091A KR19950057091A KR970055453A KR 970055453 A KR970055453 A KR 970055453A KR 1019950057091 A KR1019950057091 A KR 1019950057091A KR 19950057091 A KR19950057091 A KR 19950057091A KR 970055453 A KR970055453 A KR 970055453A
Authority
KR
South Korea
Prior art keywords
resistor
watchdog timer
output
divider
mos transistor
Prior art date
Application number
KR1019950057091A
Other languages
Korean (ko)
Inventor
김종준
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950057091A priority Critical patent/KR970055453A/en
Publication of KR970055453A publication Critical patent/KR970055453A/en

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Abstract

본 발명은 워치독 타이머에 관해 게시한다. 종래의 워치독 타이머는 카운터를 이용함으로써 반도체 장치에 내장될 경우, 많은 면적을 차지하였으나 본 발명의 워치독 타이머는 저항과 캐패시터를 사용함으로써 반도체 장치의 면적을 축소시킬 수 있다.The present invention discloses a watchdog timer. When a conventional watchdog timer is embedded in a semiconductor device by using a counter, the watchdog timer of the present invention can reduce the area of the semiconductor device by using a resistor and a capacitor.

Description

워치독 타이머Watchdog timer

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 워치독 타이머의 회로도.2 is a circuit diagram of the watchdog timer of the present invention.

Claims (2)

클럭을 입력으로 하는 분주기; 상기 분주기에 연결되며 입력에는 전원전압 및 출력에는 저항이 연결된 전송게이트; 상기 저항에 병렬로 연결된 캐패시터; 상기 저항에 연결된 모스트랜지스터; 상기 모스트랜지스터의 게이트에 연결되고 입력으로 RESET과 CLEAR신호를 갖는 제1논리게이트; 상기 저항에 연결된 버퍼; 및 상기 버퍼와 ENABLE신호를 입력으로 하고 시스템을 리셋시키는 출력신호인 NRESET를 출력으로 갖는 제2논리세이트를 구비하는 것을 특징으로 하는 워치독 타이머.A divider for receiving a clock; A transmission gate connected to the divider and having a power supply voltage connected to an input thereof and a resistor connected to an output thereof; A capacitor connected in parallel to the resistor; A MOS transistor coupled to the resistor; A first logic gate connected to the gate of the MOS transistor and having RESET and CLEAR signals as inputs; A buffer coupled to the resistor; And a second logical state having an output of NRESET, which is an output signal for inputting the buffer and the ENABLE signal and resetting the system. 제1항에 있어서, 상기 저항은 복수개인 것을 특징으로 하는 워치독 타이머.The watchdog timer according to claim 1, wherein the resistance is plural. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950057091A 1995-12-26 1995-12-26 Watchdog timer KR970055453A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950057091A KR970055453A (en) 1995-12-26 1995-12-26 Watchdog timer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950057091A KR970055453A (en) 1995-12-26 1995-12-26 Watchdog timer

Publications (1)

Publication Number Publication Date
KR970055453A true KR970055453A (en) 1997-07-31

Family

ID=66618409

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950057091A KR970055453A (en) 1995-12-26 1995-12-26 Watchdog timer

Country Status (1)

Country Link
KR (1) KR970055453A (en)

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