KR970049526A - Reset generation circuit - Google Patents

Reset generation circuit Download PDF

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Publication number
KR970049526A
KR970049526A KR1019950058888A KR19950058888A KR970049526A KR 970049526 A KR970049526 A KR 970049526A KR 1019950058888 A KR1019950058888 A KR 1019950058888A KR 19950058888 A KR19950058888 A KR 19950058888A KR 970049526 A KR970049526 A KR 970049526A
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KR
South Korea
Prior art keywords
output
gate
data
registers
latch
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KR1019950058888A
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Korean (ko)
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KR0161863B1 (en
Inventor
심재철
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문정환
Lg 반도체주식회사
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Priority to KR1019950058888A priority Critical patent/KR0161863B1/en
Publication of KR970049526A publication Critical patent/KR970049526A/en
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Publication of KR0161863B1 publication Critical patent/KR0161863B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0793—Remedial or corrective actions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24—Resetting means

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Microcomputers (AREA)
  • Electronic Switches (AREA)

Abstract

본 발명은 사용자의 잘못된 프로그램에 내부 폭주시 IC내의 레지스터들을 리셋시키는 리셋트 발생회로에 관한 것으로서, 특히 집적회로 내부의 폭주를 감지하는 폭주 감지부와, 데이타 버스를 통해 데이타가 입력되면 클럭에 동기되어 입력된 데이타를 출력하고 내부 리셋트 신호에 의해 클리어되는 D 플립플롭과, 상기 폭주 감지부의 반전 출력과 상기 D 플립플롭의 출력을 논리 조합하는 앤드 게이트와, 상기 앤드 게이트의 출력을 소정시간 래치시키는 R-S 래치와, 상기 R-S 래치의 반적 출력에 의해 초기화되는 N(여기서, N은자연수)개의 레지스터로 이루어진 데이타 레지스터와, 일측은 공통으로 접지되고 일측은 상기 데이타 레지스터의 N개의 Q 출력단에 각각 연결되는 N개의 배타적 노아 게이트와, 배타적 노아 게이트의 출력에 의해 각각 턴온/턴오프되는 직렬 결합의 N개의 N모스 트랜지스터와, 상기 배타적 노아 게이트의 출력에 의해 각각 턴온/턴오프되는 병렬 결합의 N개의 P모스 트랜지스터로 구성되고 상기 N모스 트랜지스터의 드레인단과 P모스 트랜지스터의 소오스단은 공통으로 상기 R-S 래치의 셋트단에 인버터를 통해 연결되어, IC폭주시 IC내의 모든 레지스터들이 초기화될때까지 내부 리셋트 신호를 지연시킴으로써, IC의 고집적, 대용량화에 따라 칩의 사이즈가 커져 상기 내부 리셋트 신호에 의해 초기화되어야 하는 레지스터의 숫자가 많아져도 내부 리셋트 신호의 펄스폭의 감쇠없이 IC내의 레지스터들을 모두 정확하게 리셋시킬 수 있다.The present invention relates to a reset generation circuit for resetting the registers in the IC when the internal runaway to the user's wrong program, in particular a runaway detector for detecting runaway in the integrated circuit, and synchronized with the clock when data is input through the data bus Outputs the input data and is cleared by an internal reset signal, an AND gate configured to logically combine an inverted output of the congestion detecting unit and an output of the D flip-flop, and latches the output of the AND gate for a predetermined time. And a data register consisting of N registers (where N is a natural number), which is initialized by the RS output of the RS latch, and one side is commonly grounded, and one side is connected to each of the N Q output terminals of the data register. N exclusive Noah gates and the outputs of the exclusive Noah gates are turned on and off respectively. Is composed of N N-MOS transistors in series coupling and N P-MOS transistors in parallel coupling turned on / off by an output of the exclusive NOR gate, respectively, and a drain terminal of the N-MOS transistor and a source terminal of the P-MOS transistor are It is commonly connected to the set terminal of the RS latch through an inverter, and delays the internal reset signal until all registers in the IC are initialized during IC congestion, thereby increasing the size of the chip according to the high integration and large capacity of the IC. Even if the number of registers to be initialized by the signal is large, all registers in the IC can be accurately reset without attenuation of the pulse width of the internal reset signal.

Description

리셋트 발생회로Reset generation circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명에 따른 리셋트 발생 회로도.3 is a reset generation circuit diagram according to the present invention.

제4도는 상기 제3도의 각 부의 동작 파형도.4 is an operational waveform diagram of each part of FIG.

Claims (1)

집적회로 내부의 폭주를 감지하는 폭주 감지부와, 데이타 버스를 통해 데이타가 입력되면 클럭에 동기되어 입력된 데이타를 출력하고 내부 리셋트 신호에 의해 클리어되는 D 플립플롭과, 상기 폭주 감지부의 반전 출력과 상기 D 플립플롭의 출력을 논리 조합하는 앤드 게이트로 구성되는 내부 리셋트 발생 회로에 있어서, 상기 앤드 게이트의 출력단에 리셋단이 연결되어 셋트단으로 하이신호가 입력될때까지 상기 앤드 게이트의 출력을 래치시키는 R-S 래치와, 상기 R-S 래치의 출력을 반전시켜 내부 리셋트 신호를 발생하는 인버터와, 상기 인버터에서 출력되는 내부 리셋트 신호에 의해 초기화되는 N(여기서, N은 자연수)개의 레지스터로 이루어진 데이타 레지스터와, 일측은 공통으로 접지되고 일측은 상기 데이타 레지스터의 N개의 Q출력단에 각각 연결되는 N개의 배타적 노아 게이트와, 배타적 노아 게이트의 출력에 의해 각각 턴온/턴오프되는 직렬결합의 N개의 N모스 트랜지스터와, 상기 배타적 노아 게이트의 출력에 의해 각각 턴온/턴오프되는 병렬 결합의 N개의 P모스 트랜지스터를 포함하고, 상기 N모스 트랜지스터의 드레인단과 P모스 트랜지스터의 소오스단은 공통으로 상기 R-S 래치의 셋트단에 인버터를 통해 연결됨을 특징으로 하는 리셋트 발생회로.A congestion detecting unit for detecting congestion in the integrated circuit, a D flip-flop which outputs the input data in synchronization with a clock when the data is input through the data bus, and is cleared by an internal reset signal, and an inverted output of the congestion detecting unit And an AND gate configured to logically combine the output of the D flip-flop, wherein the reset gate is connected to an output terminal of the AND gate, and the output of the AND gate is input until a high signal is input to the set terminal. Data comprising an RS latch to latch, an inverter that inverts the output of the RS latch to generate an internal reset signal, and N registers initialized by an internal reset signal output from the inverter, where N is a natural number. A resistor and one side are commonly grounded, and one side is respectively connected to the N Q output terminals of the data register. Are N exclusive NOR gates, N NMOS transistors in series each turned on / off by an output of the exclusive Noah gate, and N N of parallel couplings each turned on / off by an output of the exclusive Noah gate. And a PMOS transistor, wherein the drain terminal of the NMOS transistor and the source terminal of the PMOS transistor are commonly connected to the set terminal of the RS latch through an inverter. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950058888A 1995-12-27 1995-12-27 Reset generator KR0161863B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950058888A KR0161863B1 (en) 1995-12-27 1995-12-27 Reset generator

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Application Number Priority Date Filing Date Title
KR1019950058888A KR0161863B1 (en) 1995-12-27 1995-12-27 Reset generator

Publications (2)

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KR970049526A true KR970049526A (en) 1997-07-29
KR0161863B1 KR0161863B1 (en) 1999-01-15

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100471137B1 (en) * 1997-10-31 2005-06-07 삼성전자주식회사 Data processor having reduced register-clear-instruction execution cycles
KR100519285B1 (en) * 1998-03-20 2005-11-25 엘지전자 주식회사 Apparatus and method for delaying bus reset

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100471137B1 (en) * 1997-10-31 2005-06-07 삼성전자주식회사 Data processor having reduced register-clear-instruction execution cycles
KR100519285B1 (en) * 1998-03-20 2005-11-25 엘지전자 주식회사 Apparatus and method for delaying bus reset

Also Published As

Publication number Publication date
KR0161863B1 (en) 1999-01-15

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