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Application filed by 문정환, 금성일렉트론 주식회사filedCritical문정환
Priority to KR1019910000202ApriorityCriticalpatent/KR920015724A/en
Publication of KR920015724ApublicationCriticalpatent/KR920015724A/en
입출력 커플링 감소 풀 업/다운 회로I / O Coupling Reduction Pull-Up / Down Circuit
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제2도는 종래의 타이밍도.2 is a conventional timing diagram.
Claims (1)
입력 노드(a)와 출력단에 연결된 모스 트랜지스터의 크기를 나누어 병렬 연결함에 의해 커플링 캐패시턴스를 분산시킴으로써 래치업을 방지하도록한 것을 특징으로 하는 입출력 감소 풀 업/다운 회로.An input / output reduction pull-up / down circuit characterized by preventing the latch-up by distributing the coupling capacitance by dividing the size of the MOS transistors connected to the input node (a) and the output terminal in parallel.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910000202A1991-01-091991-01-09
I / O Coupling Reduction Pull-Up / Down Circuit
KR920015724A
(en)