KR970023833A - 반도체소자의 절연방법 - Google Patents
반도체소자의 절연방법 Download PDFInfo
- Publication number
- KR970023833A KR970023833A KR1019950036330A KR19950036330A KR970023833A KR 970023833 A KR970023833 A KR 970023833A KR 1019950036330 A KR1019950036330 A KR 1019950036330A KR 19950036330 A KR19950036330 A KR 19950036330A KR 970023833 A KR970023833 A KR 970023833A
- Authority
- KR
- South Korea
- Prior art keywords
- film
- insulating film
- polysilicon
- interlayer insulating
- forming
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 7
- 239000004065 semiconductor Substances 0.000 title claims abstract description 6
- 238000009413 insulation Methods 0.000 title 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract 6
- 229920005591 polysilicon Polymers 0.000 claims abstract 6
- 238000005530 etching Methods 0.000 claims abstract 5
- 238000001020 plasma etching Methods 0.000 claims abstract 3
- 239000002184 metal Substances 0.000 claims abstract 2
- 239000011229 interlayer Substances 0.000 claims 4
- 229920002120 photoresistant polymer Polymers 0.000 claims 2
- 239000000758 substrate Substances 0.000 claims 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 239000010410 layer Substances 0.000 claims 1
- 238000000059 patterning Methods 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Abstract
본 발명은 반도체 장치의 제조방법에 관한 것으로서, 특히 폴리실리콘과 금속막 사이의 절연 특성을 개선시키는 반도체 장치의 절연막 형성 방법에 관한 것이다.
발명은 등방성식각 특성을 이용하여 절연 특성을 개선하는 제조방법으로서 얇은 절연막을 이용하여 절연막 아래의 폴리실리콘 막질을 언터컷 단면으로 만드는 플라즈마 식각공정과, 플라즈마 식각 설비에서 SF6, CF, NF3, O2GAS를 혼합하여 폴리실리콘을 등방성 식각하는 공정과, 플라즈마 식각설비에서 등방성식각 특성을 이용하여 반도체 웨이퍼의 임계영역을 제어하는 공정을 포함한다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1A도 내지 제1D도는 본 발명에 따른 반도체 장치의 절연막 형성방법을 공정 순서대로 나타낸 단면도.
Claims (2)
- 반도체기판 상에 폴리실리콘막을 도포 후 폴리실리콘산화막 또는 고온 산화막과 같은 제1층간절연막을 얇게 형성하는 공정과, 제1층간절연막을 포토레시스트 패턴작업 후 식각하는 공정과, 언더컷을 형성하기 위해 폴리실리콘막을 등방성 플라즈마식각하는 공정과, 포토레시트막을 제거한 후 제2층간절연막을 기판 전면에 도포하고 제2층간절연막 상부에 금속막을 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.
- 제1항에 있어서, 상기 폴리실리콘막의 등방성 식각공정은 SF6, CF, NF3, O2혼합GAS를 이용하여 수행되는 것을 특징으로 하는 반도체 소자의 제조방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950036330A KR0153493B1 (ko) | 1995-10-20 | 1995-10-20 | 반도체소자의 절연방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950036330A KR0153493B1 (ko) | 1995-10-20 | 1995-10-20 | 반도체소자의 절연방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR970023833A true KR970023833A (ko) | 1997-05-30 |
KR0153493B1 KR0153493B1 (ko) | 1998-12-01 |
Family
ID=19430769
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950036330A KR0153493B1 (ko) | 1995-10-20 | 1995-10-20 | 반도체소자의 절연방법 |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR0153493B1 (ko) |
-
1995
- 1995-10-20 KR KR1019950036330A patent/KR0153493B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR0153493B1 (ko) | 1998-12-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR970023833A (ko) | 반도체소자의 절연방법 | |
US6828250B1 (en) | Process for etching vias in organosilicate glass materials without causing RIE lag | |
KR960002554A (ko) | 반도체소자의 게이트전극 형성방법 | |
KR950021107A (ko) | 콘택홀 형성방법 | |
KR960002744A (ko) | 반도체 소자의 소자분리막 형성방법 | |
KR940001268A (ko) | 반도체 소자의 자기정렬 콘택형성방법 | |
KR960002742A (ko) | 반도체소자의 제조방법 | |
KR970054070A (ko) | 반도체 장치의 커패시터 형성 방법 | |
KR960030327A (ko) | 반도체 소자의 콘택홀 형성방법 | |
KR960002714A (ko) | 반도체소자의 소자분리절연막 형성방법 | |
KR980005474A (ko) | 반도체 소자 제조방법 | |
KR980005651A (ko) | 반도체 장치의 콘택홀 형성방법 | |
KR960002547A (ko) | 반도체 소자의 콘택홀 형성방법 | |
KR960002562A (ko) | 반도체소자의 콘택홀 형성방법 | |
KR960043019A (ko) | 반도체소자의 게이트산화막 형성방법 | |
KR950014973A (ko) | 반도체소자의 미세콘택 형성방법 | |
KR940010366A (ko) | 반도체 소자의 콘택홀 제조방법 | |
KR970003613A (ko) | 반도체소자의 트랜지스터 형성방법 | |
KR920003460A (ko) | 반도체 집적회로의 소자 분리 방법 | |
KR970053372A (ko) | 반도체소자의 소자분리막 제조방법 | |
KR970030355A (ko) | 고신뢰성 비아콘택 형성을 위한 금속층간 절연막 형성방법 | |
KR970077456A (ko) | 반도체 소자의 콘택 홀 형성 방법 | |
KR970018180A (ko) | 반도체 소자 제조방법 | |
KR940022787A (ko) | 반도체 소자 절연방법 | |
KR19990031661A (ko) | 반도체 기판 식각방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20100630 Year of fee payment: 13 |
|
LAPS | Lapse due to unpaid annual fee |