KR970023716A - Manufacturing Method of Semiconductor Device - Google Patents

Manufacturing Method of Semiconductor Device Download PDF

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Publication number
KR970023716A
KR970023716A KR1019950035618A KR19950035618A KR970023716A KR 970023716 A KR970023716 A KR 970023716A KR 1019950035618 A KR1019950035618 A KR 1019950035618A KR 19950035618 A KR19950035618 A KR 19950035618A KR 970023716 A KR970023716 A KR 970023716A
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KR
South Korea
Prior art keywords
forming
substrate
contact pad
semiconductor device
polysilicon film
Prior art date
Application number
KR1019950035618A
Other languages
Korean (ko)
Inventor
윤여철
박영호
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950035618A priority Critical patent/KR970023716A/en
Publication of KR970023716A publication Critical patent/KR970023716A/en

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Abstract

본 발명은 반도체장치 금속 접속구의 불순물 영역과 금속배선을 연결하는 콘택 패드(contact pad) 형성 방법에 관한 것으로, 기판상에 게이트전극을 형성하는 공정과; 상기 기판상에 불순물 이온을 주입하여 소스/드레인 영역으로 작용되는 P형 불순물 영역을 형성하는 공정과; 상기 기판상에 T1을 포함한 P+형 폴리실리콘막을 형성하고 패터닝하여 콘택패드를 형성하는 공정과; 상기 콘택패드 및 기판상에 층간절연막을 형성하는 공정과; 상기 층간절연막을 습식 및 건식식각하여 접속구를 형성하는 공정을 포함하고 있다.The present invention relates to a method of forming a contact pad for connecting an impurity region of a semiconductor device metal connection port and a metal wiring, the method comprising: forming a gate electrode on a substrate; Implanting impurity ions onto the substrate to form a P-type impurity region acting as a source / drain region; Forming a contact pad by forming and patterning a P + type polysilicon film including T1 on the substrate; Forming an interlayer insulating film on the contact pad and the substrate; And forming a connection hole by wet and dry etching the interlayer insulating film.

Description

반도체장치의 제조방법Manufacturing Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2A도 내지 제2D도는 본 발명의 실시예에 따른 반도체장치의 금속 접속구 형성 공정 단면도.2A to 2D are cross-sectional views of a metal connector forming process of a semiconductor device according to an embodiment of the present invention.

Claims (4)

반도체 기판(11)상에 게이트전극(21)을 형성하는 공정과; 상기 기판(11)상에 BF2불순물 이온을 주입하여 P+형 불순물 영역을 형성하는 공정과; 상기 게이트전극(21) 및 기판(11)상에 3가의 T1을 포함한 P+형 폴리실리콘막(41)을 형성하는 공정과; 상기 P+형 폴리실리콘막(41)을 패터닝하여 콘택 패드(41a) 패턴으로 형성하는 공정과; 상기 콘택 패드(41a) 및 상기 기판(11)상에 층간절연막(51)을 형성하는 공정과; 상기 층간절연막(51)을 습식 및 건식하여 금속 접속구를 형성하는 공정을 포함하는 것을 특징으로 하는 반도체 장치의 금속 접속구 형성 방법.Forming a gate electrode 21 on the semiconductor substrate 11; Implanting BF 2 impurity ions onto the substrate (11) to form a P + type impurity region; Forming a P + type polysilicon film (41) including a trivalent T1 on the gate electrode (21) and the substrate (11); Patterning the P + type polysilicon film (41) to form a contact pad (41a) pattern; Forming an interlayer insulating film (51) on said contact pad (41a) and said substrate (11); And forming a metal connector by wet and dry the interlayer insulating film (51). 제 1 항에 있어서, 상기 P+형 폴리실리콘막(41)내의 T1은 전체 대비 0.03atomic%인 것을 특징으로 하는 반도체 장치의 금속 접속구 형성방법.2. The method for forming a metal connector of a semiconductor device according to claim 1, wherein T1 in said P + type polysilicon film (41) is 0.03 atomic% of the total. 제 1 항에 있어서, 상기 P+형 폴리실리콘막(41)은 Ar스퍼터 방법으로 형성하는 것을 특징으로 하는 반도체장치의 금속 접속구 형성 방법.2. The method for forming a metal connector of a semiconductor device according to claim 1, wherein the P + type polysilicon film is formed by an Ar sputtering method. 제 1 항에 있어서, 상기 p+형 폴리실리콘막(41)을 이용한 콘택 패드(41a)의 두께를 1000-5000Å으로 형성하는 것을 특징으로 하는 반도체장치의 금속 접속구 형성 방법.2. The method for forming a metal connector of a semiconductor device according to claim 1, wherein the thickness of the contact pad (41a) using said p + type polysilicon film (41) is formed to be 1000-5000 kPa. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950035618A 1995-10-16 1995-10-16 Manufacturing Method of Semiconductor Device KR970023716A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950035618A KR970023716A (en) 1995-10-16 1995-10-16 Manufacturing Method of Semiconductor Device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950035618A KR970023716A (en) 1995-10-16 1995-10-16 Manufacturing Method of Semiconductor Device

Publications (1)

Publication Number Publication Date
KR970023716A true KR970023716A (en) 1997-05-30

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950035618A KR970023716A (en) 1995-10-16 1995-10-16 Manufacturing Method of Semiconductor Device

Country Status (1)

Country Link
KR (1) KR970023716A (en)

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