KR970013733A

KR970013733A - Input buffer circuit

Info

Publication number: KR970013733A
Application number: KR1019950025480A
Authority: KR
Inventors: 여협구
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1995-08-18
Filing date: 1995-08-18
Publication date: 1997-03-29

Abstract

1. 청구범위에 기재된 기술 분야; 입력버퍼회로에 관한 것으로, 특히 입력단으로 들어오는 신호가 계속 변화하더라도 입력버퍼를 제어하여 전력소모를 줄일 수 있는 입력버퍼회로에 관한 것임.1. the technical field described in the claims; The present invention relates to an input buffer circuit, and more particularly, to an input buffer circuit that can reduce power consumption by controlling an input buffer even when a signal input to the input terminal is constantly changing.

2. 발명에서 해결하고자 하는 기술적 과제; 양방향 출력버퍼에서 출력 동작이 이루어지는 상태에서 입력되는 자체의 전력 소모를 줄일 수 있는 회로를 제공함.2. The technical problem to be solved in the invention; Provides a circuit that can reduce power consumption of the input while the output operation is performed in the bidirectional output buffer.

3. 발명의 해결방법의 요지; 입력에 들어오는 신호가 계속 변하더라도 내부 논리신호에 의해 입력버퍼를 제어하여 전력 소모를 하지 않을 수 있도록 입력버퍼를 구성하되, 상기 입력버퍼의 제어를 3-스테이트로 제어하여 내부로 들어가는 신호가 인식되어지지 않아도 3-스테이트 상태를 그대로 유지시켜 후에 내부로 들어가는 신호가 하이(or로우)로 발생시 입력버퍼 자체의 전력소모 뿐아니라, 내부 논리신호의 전력을 최소화 할 수 있도록 구성되어짐을 특징으로 한다.3. Summary of the Solution of the Invention; The input buffer is configured not to consume power by controlling the input buffer by the internal logic signal even if the incoming signal keeps changing, but the signal entering the inside is controlled by controlling the control of the input buffer to 3-state. It is configured to minimize the power of the internal logic signal as well as the power consumption of the input buffer itself when the signal entering the inside is maintained high (or low) even if it is not supported.

4. 발명의 용도 : 입력 버퍼회로.4. Purpose of the invention: Input buffer circuit.

Description

Input buffer circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 회로도.2 is a circuit diagram according to the present invention.

제3도는 제1도와 제3도에 의한 출력 비교 특성도.3 is an output comparison characteristic diagram according to FIG. 1 and FIG.

Claims

An input buffer comprising: first means for controlling power consumption by controlling an input buffer by an internal logic signal even if a signal input to the input buffer continues to change; and controlling the input buffer to the first means. Control by 3-state to keep the 3-state state as it is, even if the signal is not recognized.If the signal to go inside is high or low, it is generated according to the power consumption of the input buffer itself or the internal logic signal. An input buffer circuit, characterized in that consisting of a second means for eliminating the power consumption.

A source end of the PMOS transistor 101 in an input buffer connected to a gate of an inverter type N, PMOS transistors 101 and 102 from a pad PAD, and outputting to a source drain end of the N and PMOS transistors 101 and 102. A drain of the PMOS transistor 201 is connected to the drain of the PMOS transistor 201, and a gate of the PMOS transistor 201 is connected to ground (Vss), and a drain of the NMOS transistor 202 is connected to a source terminal of the NMOS transistor 102. N, the input terminal of the NAND gate 203 is connected to the source-drain connection terminal of the PMOS transistors 101 and 102, and the input control terminal C is connected to the type force terminal of the NAND gate 203 and the NMOS transistor 202. And an input buffer circuit configured to minimize current flow to N, PMOS transistors (101, 102) in a normal or three-state state by a control signal of a control stage (C) connected to a gate stage.

※ Note: The disclosure is based on the initial application.