KR970019074A

KR970019074A - Control latch circuit in input buffer

Info

Publication number: KR970019074A
Application number: KR1019950029239A
Authority: KR
Inventors: 여협구
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1995-09-06
Filing date: 1995-09-06
Publication date: 1997-04-30

Abstract

1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION

입력버퍼에 있어서 제어 래치회로에 관한 것임.The control latch circuit in the input buffer.

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

입력의 동작이 필요없을때 제어단으로 입력되는 제어신호에 의해 입력의 동작을 디스에이블시켜 전력 소모를 없게함과 동시에 이전의 출력상태 값을 그대로 유지고정시키는 회로를 제공하고, 출력부의 이전 데이타의 래치 상태의 인버터의 크기를 갖하여 버퍼링하는 출력과 반전 동작을 하는 출력을 갖게하는 회로를 제공함.Provides a circuit that disables the operation of the input by the control signal input to the control stage when the operation of the input is not necessary, thereby eliminating power consumption and maintaining and fixing the previous output state value. Provides a circuit that has the size of an inverter in a latched state and has an output for buffering and an output for inverting operation.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

N, P모스 트랜지스터(101, 102)에 의한 입력수단과, 인버터(103) 및 낸드게이트(104)에 의한 출력수단을 구비한 입력버퍼에 있어서, 입력단(PAD)으로부터 N, P모스 트랜지스터(101, 102)의 입력의 동작이 필요없을때 N, P모스트랜지스터(101, 102)를 통해 흐르는 전류를 차단토록 3-스테이트 기능을 가지는 제1수단과, 상기 제1수단의 상태에 따라 상기 입력수단의 출력되는 신호를 정상모드에서 전달하되, 래치모드에서는 차단되는 제2수단과, 제어단(C)으로 입력되는 래치 또는 정상모드 입력신호를 받는 제3수단과, 상기 래치 또는 정상모드입력신호를 변환하여 각부를 제어하는 제4수단과, 상기 제1수단의 상태에 따라 상기 입력수단의 출력되는 신호를 래치모드에서 이전상태를 유지하고 정상모드에서는 오프되는 제5수단으로 구성됨.In an input buffer including an input means by the N, P-MOS transistors 101 and 102, and an output means by the inverter 103 and the NAND gate 104, an N, P-MOS transistor 101 from an input terminal PAD. First means having a 3-state function to block the current flowing through the N and P MOS transistors 101 and 102 when no operation of the input of the first and second inputs is required; The second means for transmitting the output signal in the normal mode, but blocked in the latch mode, the third means for receiving a latch or normal mode input signal input to the control stage (C), and the latch or the normal mode input signal And fourth means for converting and controlling the respective parts, and fifth means for maintaining the previous state in the latch mode and off in the normal mode according to the state of the first means.

4. 발명의 중요한 용도4. Important uses of the invention

입력 버퍼회로Input buffer circuit

선택도 : 제 2 도Selectivity: 2nd degree

Description

Control latch circuit in input buffer

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 종래의 입력 버퍼 회로도,1 is a conventional input buffer circuit diagram,

제2도는 본 발명에 따른 회로도,2 is a circuit diagram according to the present invention,

제3도는 제2도의 동작 파형도.3 is an operational waveform diagram of FIG.

Claims

In an input buffer including an input means by the N, P-MOS transistors 101 and 102, and an output means by the inverter 103 and the NAND gate 104, an N, P-MOS transistor 101 from an input terminal PAD. First means having a 3-state function to block the current flowing through the N and P MOS transistors 101 and 102 when no operation of the input of the first and second inputs is required; The second means for transmitting the output signal in the normal mode, but blocked in the latch mode, the third means for receiving the latch or normal mode input signal input to the control stage (C), and the latch or normal mode input signal And fourth means for controlling each part by converting the second means, and fifth means for maintaining the previous state in the latch mode and off in the normal mode according to the state of the first means. Input buffer.

The NMOS transistor 102 of claim 1, wherein a first means connects the source terminal of the P MOS transistor 201 to the drain terminal of the P MOS transistor 101, and the NMOS transistor 102 to the drain terminal of the P MOS transistor 201. And a drain and a drain of the N MOS transistor (102) to a source end of the N MOS transistor (202) so as to be driven by the third and fourth means.

The input buffer according to claim 1, wherein the fourth means is constituted by an inverter (205).

The N and P MOS transistors 206 and 207 controlled by the third and fourth means and the outputs of the second means are inverted. And an inverter (103, 208) provided to the (207).

※ Note: The disclosure is based on the initial application.