KR970008535B1 - 배치요소 배치설계 시스템 - Google Patents

배치요소 배치설계 시스템 Download PDF

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Publication number
KR970008535B1
KR970008535B1 KR1019920018978A KR920018978A KR970008535B1 KR 970008535 B1 KR970008535 B1 KR 970008535B1 KR 1019920018978 A KR1019920018978 A KR 1019920018978A KR 920018978 A KR920018978 A KR 920018978A KR 970008535 B1 KR970008535 B1 KR 970008535B1
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KR
South Korea
Prior art keywords
arrangement
area
data
cell
unit
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KR1019920018978A
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English (en)
Korean (ko)
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KR930009077A (ko
Inventor
류우스께 마스오까
Original Assignee
후지쓰 가부시끼가이샤
세끼자와 다다시
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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Architecture (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
KR1019920018978A 1991-10-15 1992-10-15 배치요소 배치설계 시스템 Expired - Fee Related KR970008535B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP3266105A JP2601586B2 (ja) 1991-10-15 1991-10-15 配置要素の配置配線方法
JP91-266105 1991-10-15

Publications (2)

Publication Number Publication Date
KR930009077A KR930009077A (ko) 1993-05-22
KR970008535B1 true KR970008535B1 (ko) 1997-05-24

Family

ID=17426387

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920018978A Expired - Fee Related KR970008535B1 (ko) 1991-10-15 1992-10-15 배치요소 배치설계 시스템

Country Status (5)

Country Link
US (1) US5475608A (enExample)
EP (1) EP0538035B1 (enExample)
JP (1) JP2601586B2 (enExample)
KR (1) KR970008535B1 (enExample)
DE (1) DE69232026T2 (enExample)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5691913A (en) * 1994-03-28 1997-11-25 Matsushita Electric Ind. Co. Layout designing apparatus for circuit boards
US5640328A (en) * 1994-04-25 1997-06-17 Lam; Jimmy Kwok-Ching Method for electric leaf cell circuit placement and timing determination
US5535134A (en) * 1994-06-03 1996-07-09 International Business Machines Corporation Object placement aid
US5619419A (en) * 1994-09-13 1997-04-08 Lsi Logic Corporation Method of cell placement for an itegrated circuit chip comprising integrated placement and cell overlap removal
JPH08235150A (ja) * 1995-02-24 1996-09-13 Fujitsu Ltd シミュレーティド・アニーリングによる次候補生成装置および方法
US6516307B1 (en) 1995-02-24 2003-02-04 Fujitsu Limited Next alternative generating apparatus using simulated annealing and method thereof
US5796625A (en) * 1996-03-01 1998-08-18 Lsi Logic Corporation Physical design automation system and process for designing integrated circuit chip using simulated annealing with "chessboard and jiggle" optimization
JP3204381B2 (ja) * 1997-11-04 2001-09-04 エヌイーシーマイクロシステム株式会社 半導体装置の自動配置配線方法
US6099583A (en) * 1998-04-08 2000-08-08 Xilinx, Inc. Core-based placement and annealing methods for programmable logic devices
US6898773B1 (en) * 2002-01-22 2005-05-24 Cadence Design Systems, Inc. Method and apparatus for producing multi-layer topological routes
JP2003076734A (ja) * 2001-09-03 2003-03-14 Fujitsu Ltd 集積回路設計装置及び集積回路設計方法並びにプログラム
US6782518B2 (en) * 2002-03-28 2004-08-24 International Business Machines Corporation System and method for facilitating coverage feedback testcase generation reproducibility
US7113945B1 (en) * 2002-04-10 2006-09-26 Emc Corporation Virtual storage device that uses volatile memory
US7340489B2 (en) * 2002-04-10 2008-03-04 Emc Corporation Virtual storage devices
US7526739B2 (en) * 2005-07-26 2009-04-28 R3 Logic, Inc. Methods and systems for computer aided design of 3D integrated circuits
US7404166B2 (en) * 2005-10-24 2008-07-22 Lsi Corporation Method and system for mapping netlist of integrated circuit to design
EP3274828B1 (en) * 2015-03-24 2020-05-06 Telefonaktiebolaget LM Ericsson (publ) Methods and nodes for scheduling data processing
CN109920787B (zh) * 2017-12-12 2021-05-25 中芯国际集成电路制造(北京)有限公司 互连结构的设计方法、装置及制造方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1502554A (enExample) * 1965-12-01 1968-02-07
US4630219A (en) * 1983-11-23 1986-12-16 International Business Machines Corporation Element placement method
JPS60114968A (ja) * 1983-11-28 1985-06-21 Hitachi Ltd 推論システム
US4700316A (en) * 1985-03-01 1987-10-13 International Business Machines Corporation Automated book layout in static CMOS
US4918614A (en) * 1987-06-02 1990-04-17 Lsi Logic Corporation Hierarchical floorplanner
JPH02242474A (ja) * 1989-03-16 1990-09-26 Hitachi Ltd 素子配置最適化方法及び装置並びに最適配置判定方法及び装置
DE69033724T2 (de) * 1989-12-04 2001-11-29 Matsushita Electric Industrial Co., Ltd. Plazierungsoptimierungssystem mit Hilfe von CAD
US5208759A (en) * 1990-12-13 1993-05-04 Vlsi Technology, Inc. Method for placement of circuit components in an integrated circuit

Also Published As

Publication number Publication date
DE69232026D1 (de) 2001-10-04
JPH05108759A (ja) 1993-04-30
JP2601586B2 (ja) 1997-04-16
EP0538035A3 (enExample) 1994-12-28
EP0538035B1 (en) 2001-08-29
DE69232026T2 (de) 2002-01-24
US5475608A (en) 1995-12-12
EP0538035A2 (en) 1993-04-21
KR930009077A (ko) 1993-05-22

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