KR970007846B1 - Past device type semiconductor package - Google Patents
Past device type semiconductor package Download PDFInfo
- Publication number
- KR970007846B1 KR970007846B1 KR1019940004445A KR19940004445A KR970007846B1 KR 970007846 B1 KR970007846 B1 KR 970007846B1 KR 1019940004445 A KR1019940004445 A KR 1019940004445A KR 19940004445 A KR19940004445 A KR 19940004445A KR 970007846 B1 KR970007846 B1 KR 970007846B1
- Authority
- KR
- South Korea
- Prior art keywords
- chip
- lead frame
- semiconductor package
- package
- wire
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Wire Bonding (AREA)
- Die Bonding (AREA)
Abstract
Description
제1도는 종래 패키지의 와이어 본딩된 평면도.1 is a wire bonded plan view of a conventional package.
제2도는 본 발명 패키지의 와이어 본딩된 평면도.2 is a wire bonded plan view of the package of the present invention.
제3도는 본 발명 패키지의 단면도이다.3 is a cross-sectional view of the package of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
3 : 칩10,11 : 보조리드프레임3: chip 10,11: auxiliary lead frame
본 발명은 처리속도를 빠르게 하는 패스트 디바이스용 반도체 패키지에 관한 것으로, 패키지내의 칩상단에 보조리드프레임을 부착시키는 방식으로 전원을 공급해 주도록한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package for a fast device that speeds up processing speed, and provides power by attaching an auxiliary lead frame to an upper chip of the package.
일반적으로 패스트디바이스용 반도체 패키지는 제1도와 같이 리드프레임 패드(2)에 칩(3)을 어태치하며, 리드프레임(1)의 내부리드(4)는 칩(3)의 양단 위치에서 전원을 공급 받도록 와이어 본딩한다.In general, a semiconductor device for fast devices attaches the chip 3 to the lead frame pad 2 as shown in FIG. 1, and the inner lead 4 of the lead frame 1 supplies power at both ends of the chip 3. Wire bond to be supplied.
이는 리드프레임(1)에 칩(3)을 어태치하고, 어태치된칩(3)에 전원을 공급 받도록된 패드(Vcc, Vss로 표기)를 포함하여 와이어 본딩한다. 이어 몰딩하고 트림(Trim)한 후, 리드를 도금하여 포밍(Forming)한 후 패키지를 완성한다. 그러나 이경우 패스트 디바이스는 전원의 패드(Vcc,Vss) 위치가 반드시 내부리드(4)의 10, 20번핀(칩(3)의 양측)에 위치하도록 반도체의 칩(3) 디자인을 해야만이 패키지 제조가 가능하였다.This attaches the chip 3 to the lead frame 1 and wire-bonds it, including pads (denoted Vcc, Vss) to be supplied with power to the attached chip 3. After molding and trimming, the lead is plated and formed to complete the package. However, in this case, the fast device must design the chip 3 of the semiconductor so that the pads (Vcc, Vss) of the power supply must be located at pins 10 and 20 (both sides of the chip 3) of the inner lead 4. It was possible.
즉, 반도체의 특성을 살려 고유의 칩을 디자인 하여도10,20번핀 위치에 패드(Vcc,Vss)가 오지 않으면 와이어 본딩이 곤란하고, 또한 리드프레임(1)으로 와이어 본딩이 가능하도록 디자인 하기도 불가능한 어려움이 많다.That is, even if a unique chip is designed utilizing the characteristics of the semiconductor, if the pads (Vcc, Vss) do not come to the pin positions 10 and 20, wire bonding is difficult and it is impossible to design the wire bonding to the lead frame 1. There are many difficulties.
본 발명은 이를 해결하고자 하는 것으로 칩의 표면에 어느 부위에서나 전원을 공급받을 수 있도록 하는 보조리드프레임을 장착시키는 방식을 이용함을 특징으로 한다.The present invention is to solve this problem is characterized in that the use of a method of mounting the auxiliary lead frame to receive power from any part of the surface of the chip.
즉, 본 발명은 칩의 표면에 전원용 보조리드프레임을 패턴상태로 접착시키고 와이어본딩 및 몰딩하여서된 패스트 디바이스용 반도체 패키지를 제공하려는 것이다.That is, the present invention is to provide a semiconductor package for a fast device by bonding the auxiliary lead frame for the power supply to the surface of the chip in a patterned state, wire bonding and molding.
이하 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제2도는 본 발명을 설명하는 와이어본딩된 몰딩상태의 평면도, 제3도는 본발명 패키지의 단면도이다.2 is a plan view of a wire bonded molding state illustrating the present invention, and FIG. 3 is a cross sectional view of the present invention package.
본 발명은 칩의 양단에서 리드프레임과 와이어 본딩되는 패스트 디바이스용 반도체 패키지에서, 칩(3)의 표면에 전원용 보조리드프레임(10,11)을 패턴상태로 접착시키는 방식으로 임의 위치에서 와이어본딩을 가능케 하도록 이루어진다.According to the present invention, in a semiconductor device for fast devices that is wire-bonded with lead frames at both ends of the chip, wire bonding is performed at an arbitrary position by bonding the auxiliary lead frames 10 and 11 for power to the surface of the chip 3 in a pattern state. Is made possible.
이러한 원리로 패키지를 제조함에 있어서는 리드프레임패드(2)에 전원패드가 편리하게 임의로 배열된 칩(3)을 어태치하고, 칩(3) 표면에 LOC(Lead On Chip) 방식과 같이 특정패턴의 보조리드프레임(10,11)을 부착하고, 와이어 본딩을 필요에 따라 전원패드(Vcc,Vss)의 위치에 상관없이 가까운 보조리드프레임(10,11)에서 수행하며 몰딩, 트림, 도금, 포밍등의 일련의 과정을 수행하여 본 발명의 패키지를 수득가능케 된다.In manufacturing a package based on this principle, a chip 3 in which a power pad is conveniently arranged on the lead frame pad 2 is attached to the lead frame pad 2, and the surface of the chip 3 has a specific pattern such as a lead on chip (LOC) method. Auxiliary lead frames 10 and 11 are attached, and wire bonding is performed on the auxiliary lead frames 10 and 11 that are close to each other regardless of the position of the power pads (Vcc, Vss). The package of the present invention can be obtained by performing a series of procedures.
물론 상기에서 보조리드프레임(10,11)을 칩 어태치전에 미리 준비하였다가 칩 어태치한 후 보조리드프레임(10,11)을 어태치함을 알 수 있을 것이다.Of course, it will be appreciated that the auxiliary lead frames 10 and 11 are prepared in advance before the chip attach, and then the auxiliary lead frames 10 and 11 are attached after the chip attach.
이는 제3도와 같은 구조를 이루는바, 리드프레임(1)의 패드(2)에 칩(3)이 어태치하고, 칩(3)위에는 보조리드프레임(10,11)이 부착되며, 와이어 본딩 및 몰딩수지(5)에 의한 몰딩으로 패키지를 이루게 되는 것이다.It forms a structure as shown in FIG. 3, wherein the chip 3 is attached to the pad 2 of the lead frame 1, and the auxiliary lead frames 10 and 11 are attached to the chip 3, and wire bonding and The molding is achieved by molding with a molding resin (5).
이와 같은 본 발명 패키지는 와이어 본딩용 본딩수량에 관계없이 전원패드(Vcc,Vss)로 본딩할 경우 패스트 디바이스의 스피드를 현재보다 현격히 단축시킬 수 있고, 일시에 칩에서 요구하는 위치에 Vcc와 Vss를 공급할 수 있어 스피드를 가장 빠르게 할 수 있다. 보통 디바이스의 처리속도가 80㎱이고 패스트 디바이스는 50-30㎱가 대부분이나 본 발명 패키지는 10㎱ 이하로 단축시킬 수 있었다.Such a package of the present invention can significantly reduce the speed of a fast device than the present when bonding with power pads (Vcc, Vss) regardless of the amount of bonding for wire bonding, and at the time the Vcc and Vss at the position required by the chip It can be supplied for the fastest speed. In general, the processing speed of the device is 80 kW and the fast device is 50-30 kW, but the package of the present invention can be shortened to 10 kW or less.
이상과 같이 본 발명은 칩위에 보조 리드프레임을 어태치하는 방식을 이용하여 요구하는 전원패드(Vcc,Vss)에 전원을 신속히 공급할 수 있어 스피드를 가장 빠르게 처리할 수 있다.As described above, the present invention can quickly supply power to the required power pads (Vcc, Vss) using a method of attaching an auxiliary lead frame on a chip, thereby enabling the fastest speed processing.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940004445A KR970007846B1 (en) | 1994-03-08 | 1994-03-08 | Past device type semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940004445A KR970007846B1 (en) | 1994-03-08 | 1994-03-08 | Past device type semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR970007846B1 true KR970007846B1 (en) | 1997-05-17 |
Family
ID=19378506
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019940004445A KR970007846B1 (en) | 1994-03-08 | 1994-03-08 | Past device type semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR970007846B1 (en) |
-
1994
- 1994-03-08 KR KR1019940004445A patent/KR970007846B1/en not_active IP Right Cessation
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