KR970006863B1 - Active matrix lcd apparatus - Google Patents

Abstract

None.

Description

Active Matrix Liquid Crystal Display

1 is a block diagram of an ALCD showing one embodiment of the present invention.

2 is a signal voltage characteristic diagram of each part according to FIG. 1;

3 is a configuration diagram of the sample hold circuit shown in FIG.

4 is a diagram showing a driver circuit and a driving voltage waveform of the LCD panel according to FIG.

5 is a block diagram of an ALCD showing another embodiment of the present invention.

6 is a diagram showing a driver circuit and a driving voltage waveform of the LCD panel according to FIG.

7 is a block diagram of an ALCD showing a conventional embodiment.

8 is a block diagram of a digital ALCD showing another conventional embodiment.

* Explanation of symbols for main parts of the drawings

1: Sample hold circuit 2: γ

3: data inversion circuit 4: controller

7, 8: signal line 9: LCD panel

10: Vertical (V) driver circuit 11: Upper horizontal (H) driver circuit

12 lower horizontal (H) driver circuit 13 pixel electrode

14: input buffer 15: shift register

16: sample hold section 17: selector

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to an active matrix liquid crystal display device that controls pixel electrodes such as LCD panels by RGB video signals.

A conventional active matrix liquid crystal display device (hereinafter referred to as ALCD) drives an analog type or digital type driver circuit using an RGB signal as an input interface to control pixel electrodes of an LCD panel.

7 is a block diagram of an ALCD showing one such conventional embodiment. As shown in FIG. 7, the conventional ALCD has a built-in analog digital conversion circuit (hereinafter referred to as an ADC circuit: 18) and a gamma (γ) conversion circuit 2 for converting an RGB signal into a digital signal once. The controller 4a for controlling each unit by the synchronization signal HS and the vertical synchronization signal VS, and the output N12 of the ADC circuit 18 is converted to the analog signal N13 by the output N12 converted by the γ conversion circuit 2. A digital analog conversion circuit (hereinafter referred to as a DAC circuit) 19 to be converted; a data inversion circuit 3 for inputting analog signals N13 to create inverted signal data N14 and N15; and a controller 4a. Data inversion circuit 3 via LPF 5 and VCO 6, LCD panel 9 having pixel electrodes 13 arranged in a matrix, and first and second signal lines 7 and 8, respectively. Upper H driver circuit 11 and lower dry controlling the potential in the H direction of the LCD panel 9 driven in the It has the circuit 12 and, LCD panel (9) V driver circuit 10 for controlling the potential of the V direction.

First, after converting the RGB signal into a digital signal in the ADC circuit 18, the input and output conversion codes necessary for demodulating the luminance voltage characteristics of the LCD panel 9 and the video signal (which is denoted by 0.45) in advance are stored. Γ-converts digital signal N11 by using the ROM in the γ-conversion circuit 2 thus obtained. Next, the γ-converted digital signal N12 is returned to the analog signal N13 by the DAC circuit 19 again.

The analog signal N13 is code inverted as the analog signals N14 and N15 inverted from each other by the data inversion circuit 3, and the upper driver circuit 11 and the lower H driver circuit (connected above and below the LCD panel 9) 12) [Also, analog H driver]. The above is an analog ALCD.

8 is a block diagram of a digital ALCD showing another conventional embodiment. As shown in FIG. 8, it is a block diagram of a conventional digital ALCD. As shown in FIG. 8, the conventional digital ALCD has an ADC circuit 18 for analog-converting RGB signals, and a digital upper H driver circuit for inputting data N11a and N11b through signal lines 7a and 8a. 11a) and the lower H driver circuit 12a, the gradation power supply 20 which instructs the gradation to the upper H driver circuit 11a and the lower H driver circuit 12a, the LCD panel 9 as shown in FIG. A V driver circuit 10 and an ADC circuit 18, a controller 4b for controlling each driver circuit, an LPF 5 and a VCO 6 are provided. Such a digital ALCD directly inputs the output data N11a and N11b of the ADC circuit 18 into the H driver circuits 11a and 12a, and the γ conversion is supplied to the H driver circuits 11a and 12a. ) By the voltage setting.

The conventional analog ALCD described above requires 6 to 8 bits or more in the number of output bits of the ADC circuit by multi-gradation of the liquid crystal display. In addition, there is a tendency to increase the dot clock of the video signal due to the increase of the display pixels of the LCD. For example, a 1.3-megapixel LCD requires 100MHz or more as the sampling rate of the ADC circuit.

The ADC circuit which simultaneously converts at a rate of 100 MHz or more at such a bit precision of about 8 bits has a large power consumption of 0.5 to 1W. In addition, the whole apparatus becomes large and the price becomes high. Therefore, the ALCD constructed using such an ADC circuit has the drawback that it hinders the low power consumption which is a merit of the LCD, and the whole becomes large and the price increases.

In addition, in the conventional ALCD, since the DAC circuit after the? Conversion also requires an increase in bit precision and a high speed, there is a drawback that the power consumption is increased, the entire apparatus is increased, and the price is increased at the same time.

Next, the conventional digital ALCD uses less DAC circuits than the analog ALCD, and consumes lower power. However, in regard to each color, when the serial-to-parallel conversion of 1: N is performed in order to match 6 to 8 bits or more, or the operating capability of the peripheral driver (typically up to about 30 MHz), the γ of 6N to 8N bits is further increased. The digital signal after conversion must be supplied to the driver around the LCD. Therefore, the conventional digital ALCD has a drawback that it becomes complicated to drag the wiring and obstructs compactness.

An object of the present invention is to provide an ALCD which performs signal processing on an analog RGB signal without using an ADC circuit and a DAC circuit, and realizes low power consumption, compactness and low cost.

In the ALCD of the present invention, in an ALCD having a liquid crystal panel including a pixel electrode, a vertical driver circuit for driving the liquid crystal panel, and an up and down horizontal driver circuit, an RGB video signal is inputted to perform level shift and amplification for sample holding. A sample hold circuit, a γ conversion circuit for γ-converting the output signal of the sample hold circuit, a data inversion circuit for creating a signal inverted with respect to a certain voltage and a non-inverted signal by the output signal of the γ conversion circuit, It has a controller which controls each said circuit, and is comprised so that the data inversion circuit may supply the reverse phase signal from the said up-down horizontal driver circuit of the said liquid crystal panel.

Further, the ALCD of the present invention is a liquid crystal panel comprising a pixel electrode, an ALCD having a vertical driver circuit for driving the liquid crystal panel and a vertical horizontal driver circuit, and inputting an RGB video signal to perform level shift and amplification to sample. The in-phase inversion signal or the in-phase non-inverting signal for a certain voltage is generated by a sample-hold circuit to be held, a? -Conversion circuit for? -Converting the output signal of the sample-hold circuit, and an output signal of the? -Conversion circuit. It has a data inversion circuit and the controller which controls each said circuit, Comprising: The said data inversion circuit is comprised so that the in phase signal may be supplied to the said up-and-down horizontal driver circuit of the said liquid crystal panel.

Next, an embodiment of the present invention will be described with reference to the drawings. 1 is a block diagram of an ALCD showing a first embodiment of the present invention. As shown in FIG. 1, the present embodiment is similar to the conventional example of FIG. 7 described above, and the LCD panel 9 made up of the pixel electrodes 13 and the vertical V driver for driving the LCD panel 9 are shown. The circuit 10 and the upper and lower horizontal (H) driver circuits 11 and 12 are provided.

In addition to these, the present embodiment includes a sample hold circuit 1 for inputting an RGB video signal, level shifting and amplifying and holding the sample, and a γ conversion circuit 2 for γ-converting the output signal N1 of the sample hold circuit 1. ), A data inversion circuit 3 for generating a signal N4 and a non-inverting signal N5 inverted with respect to a certain voltage by the output signal N3 of the? Change circuit 2, and a controller 4 for controlling each of these circuits. ) And LPF (5) and VCO (6). In addition, the data inversion circuit 3 supplies an inverted signal to the upper and lower horizontal driver circuits 11 and 12 of the LCD panel 9 via the first signal line 7 and the second signal line 8. The sample hold circuit 1 is mounted on the semiconductor substrate 30 together with the γ conversion circuit 2.

The circuit operation in this ALCD will be described with reference to FIG. 1 and the following FIG. 2. 2 is a signal voltage characteristic diagram of each part in FIG. As shown in Figs. 1 and 2, when the RGB video signal is input to the sample hold circuit 1, it is serially and in parallel converted by sample holding after amplification (RGB write signal). The serial-parallel converted video signal N1 is corrected by the gamma conversion circuit 2 to correct the reverse gamma conversion on the imager side (transmission side) and to compensate for the luminance and voltage characteristics of the liquid crystal and output the signal N3. In the data inversion circuit 3, when half of the γ-converted signal is negligible in field through due to the gate voltage of the pixel potential, the data inversion circuit 3 inverts the voltage of the counter electrode of the LCD panel 9 and outputs the remaining signals. Output in reverse. In other words, the data inversion circuit 3 supplies the inverted signals N4 and N5 to the analog upper and lower horizontal driver circuits 11 and 12 of the LCD panel 9 with respect to the reference voltage V _com .

These signals N4 and N5 connect their polarities every write of one line. Also, the timing of sample holding in the sample holding circuit 1 and the timing of data inverting in the data inverting circuit 3 or the start pulse in the shift register (not shown) in the H and V driver circuits 10 to 12 may be used. It is controlled by a signal synchronized with the HS and VS signals at the controller 4.

3 is a configuration diagram of the sample hold circuit shown in FIG. As shown in FIG. 3, the sample hold circuit 1 inputs an RGB video signal to adjust a level or the like, and inputs a clock CLK and a start pulse S signal from the controller 4. As shown in FIG. The sample register (Sample Hold) 16, which samples the output of the input buffer 14 by the output of the shift register 15, and the sample hold unit (B) by the conversion signal SE in the controller (4). The selector 17 which selects the output of 16 and sends it to the (gamma) conversion circuit 2 is provided. In this case, only the circuit of one signal in the RGB signal is described, but in practice, such a circuit is required for each RGB signal.

In the sample hold circuit 1 as described above, the input buffer 14 first performs level shift and inverted amplification of the input RGB video signal and outputs it to the sample hold unit 16. On the other hand, when the dot clock CLK and the start pulse SP generated in synchronization with the horizontal synchronizing signal HS and the vertical synchronizing signal VS in the controller 4 are supplied to the shift register 15, the shift register 15 samples. A sampling clock is generated for the holding unit 16. Here, the video signal inverted and amplified in the input buffer 14 is sampled and held by the sampling clock from the shift register 15 in the sample hold section 16.

Further, the first half and the second half of the sample hold rows in the sample hold section 16 are paired, respectively, and are held in a latch (not shown) in the selector 17. The selector 17 converts the output of the sample hold circuit 1 by outputting the front end portion or the rear end portion of the pair of sample hold columns paired by the conversion signal SE from the controller 4. . This signal is output N3 via the γ conversion circuit 2. As described above, the sample hold circuit 1 and the? Conversion circuit 2 are mounted on the semiconductor substrate 30, but may be mounted as separate substrates. In addition, if the power consumption of the LSI is allowed, it is preferable to integrate circuits corresponding to all of the RGB signals on the same chip, but if it is not allowed for the power consumption, it is necessary to integrate each corresponding circuit of the RGB signal.

4A and 4B are LCD panel driver circuit diagrams and drive voltage waveform diagrams in FIG. 1, respectively. As shown in Figs. 4A and 4B, this driving method is a dot inversion driving method, and from the data inversion circuit 3 to the upper and lower horizontal driver circuits 11 and 12 with respect to the inverted signal N4 with respect to the inverted center voltage. N5) is sent out and the inversion and non-inversion are reversed in 1H (one horizontal scanning period).

Therefore, with respect to each pixel electrode, +,-in the data line direction (vertical direction) connected to the upper and lower horizontal driver circuits 11 and 12 and the scan line direction (lateral direction) connected to the vertical driver circuit 10, respectively. Alternates.

The dot inversion driving method is also referred to as a data line driving method. In this case, the inverted signals N4 and N5 are transmitted to the upper and lower horizontal driver circuits 11 and 12 with respect to the inverting center voltage, and at the same time inverted. Reverse the inversion at 1 V (one vertical scan period). Therefore, as for each of the appeal electrodes, the data line connected to the upper horizontal driver circuit 11 becomes +, and the data line connected to the lower horizontal driver circuit 12 becomes-.

According to this embodiment, low power consumption can be realized because signal processing such as serial / parallel conversion and? Conversion is performed without using an ADC circuit and a DAC circuit for processing an analog RGB video signal, and thus the sample hold circuit 1 By integrating the? conversion circuit 2 into one chip, compactness and low cost can be realized.

5 is a block diagram of an ALCD showing another embodiment of the present invention. As shown in FIG. 5, in the present embodiment, the data inversion circuit 3, together with the sample hold circuit 1 and the? Conversion circuit 2, is also formed on the same semiconductor substrate 40 as compared with the first embodiment described above. This is an example in which the signal lines from the data inversion circuit 3 to the upper and lower driver circuits 11 and 12 are the same. In addition, since the circuit and its operation are the same as in the first embodiment, description thereof is omitted.

6A and 6B are a driver circuit diagram and a drive voltage waveform diagram of the LCD panel in FIG. 5, respectively. As shown in Figs. 6A and 6B, this driving method is a gate line inversion driving method, and the data inverting circuit 3 sends in-phase signal N4 to the inverted center voltage from the data inverting circuit 3 to the upper and lower horizontal driver circuits 11 and 12. At the same time, the inversion / non-inversion is reversed to 1H (one horizontal number period). Therefore, the polarities of the write voltages for the pixel electrodes 13 are written with the same polarity when viewed with respect to the pixel electrodes connected to the same scan line (the line driven by the V driver circuit 10). Therefore, with respect to each pixel electrode, + and-alternate with each scan line.

This gate line inversion driving method is also referred to as a frame inversion driving method. In this case, the in-phase signal N4 is sent to the upper and lower horizontal driver circuits 11 and 12 with respect to the inversion center voltage, and at the same time, the inversion and non-inversion are reversed to 1 V (one vertical scanning period). Therefore, with respect to each pixel electrode, all the pixels + and all the pixels-are alternately made for each frame.

Also in this embodiment, since signal processing such as serial / parallel conversion and γ conversion is performed without using an ADC circuit and a DAC circuit for an analog RGB video signal, the power consumption can be reduced, and the sample hold circuit 1 and the γ conversion circuit can be realized. (2) By integrating the data inversion circuit 3 into one chip, compactness and low cost can be realized.

As described above, the ALCD of the present invention has a sample hold circuit, a gamma conversion circuit for gamma-converting the output signal of the sample hold circuit, and a signal or ratio inverted with respect to a certain voltage in accordance with the output signal of the gamma conversion circuit. It has a data inversion circuit for creating an inversion signal and a controller for controlling each circuit. The data inversion circuit uses an ADC circuit and a DAC circuit to supply a reverse or in phase signal to the upper and lower horizontal driver circuits of the LCD panel. It is possible to achieve low power consumption because it is finished without doing so. In addition, the present invention has the effect of achieving compactness and low cost by integrating the sample hold circuit and the? Conversion circuit into one chip.

Claims (9)

In an active matrix liquid crystal display device having a liquid crystal panel comprising a pixel electrode, a vertical driver circuit for driving the liquid crystal panel, and a vertical horizontal driver circuit, a sample for inputting an RGB video signal to perform level shift and amplification and hold a sample. A hold circuit, a γ conversion circuit for γ-converting the output signal of the sample hold circuit, a data inversion circuit for creating a signal inverted with respect to a certain voltage and a non-inverting signal by the output signal of the γ-conversion circuit, and An active matrix liquid crystal display device having a controller for controlling each circuit, wherein the data inversion circuit supplies an inverted signal from the upper and lower horizontal driver circuits of the liquid crystal panel. 2. The active matrix liquid crystal display device according to claim 1, wherein the inverted signal and the non-inverted signal are reversed in one horizontal scanning period in the data inversion circuit by the control of the controller. 2. The active matrix liquid crystal display device according to claim 1, wherein the inverted signal and the non-inverted signal are reversed in one vertical scanning time in the data inversion circuit by the control of the controller. 2. The apparatus of claim 1, wherein the sample hold circuit comprises: an input buffer for level shifting and amplifying the RGB video signal, a sample hold section for sample holding the amplified video signal, and a first signal from the outside; And a shift register for generating a signal for determining the sampling timing of the sample-holding portion, and a selector for selecting the sample-held signal as an external second signal. The active matrix liquid crystal display device according to claim 1, wherein the sample hold circuit and the? Conversion circuit are integrated on the same semiconductor substrate. In an active matrix liquid crystal display device having a liquid crystal panel comprising a pixel electrode, a vertical driver circuit for driving the liquid crystal panel, and a vertical horizontal driver circuit, a sample for inputting an RGB video signal to perform level shift and amplification and hold a sample. A hold circuit, a γ conversion circuit for γ-converting the output signal of the sample hold circuit, and a data inversion circuit for creating an inverted signal of in phase or non-inverted signal of in phase with respect to a certain voltage by the output signal of the γ conversion circuit. And a controller for controlling the respective circuits, wherein the data inversion circuit supplies an in-phase signal to the upper and lower horizontal driver circuits of the liquid crystal panel. 7. The active matrix liquid crystal display device according to claim 6, wherein the in-phase signal is reversed in one horizontal scanning period in the data inversion circuit by the control of the controller. The active matrix liquid crystal display device according to claim 6, wherein the in-phase signal is reversed in one vertical scanning period in the data inversion circuit by the control of the controller. 7. The active matrix liquid crystal display device according to claim 6, wherein the sample hold circuit, the? Conversion circuit, and the data inversion circuit are integrated on the same semiconductor substrate.