KR970003732B1 - Method of forming the multilayer wiring on the semiconductor device - Google Patents
Method of forming the multilayer wiring on the semiconductor device Download PDFInfo
- Publication number
- KR970003732B1 KR970003732B1 KR94000605A KR19940000605A KR970003732B1 KR 970003732 B1 KR970003732 B1 KR 970003732B1 KR 94000605 A KR94000605 A KR 94000605A KR 19940000605 A KR19940000605 A KR 19940000605A KR 970003732 B1 KR970003732 B1 KR 970003732B1
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- insulation layer
- interlayer insulation
- semiconductor device
- metal wiring
- Prior art date
Links
- 238000000034 method Methods 0.000 title abstract 6
- 239000004065 semiconductor Substances 0.000 title abstract 3
- 238000009413 insulation Methods 0.000 abstract 4
- 239000011229 interlayer Substances 0.000 abstract 4
- 239000010410 layer Substances 0.000 abstract 4
- 239000002184 metal Substances 0.000 abstract 3
- 238000005468 ion implantation Methods 0.000 abstract 2
- 238000000151 deposition Methods 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/3115—Doping the insulating layers
- H01L21/31155—Doping the insulating layers by ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76823—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. transforming an insulating layer into a conductive layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR94000605A KR970003732B1 (en) | 1994-01-14 | 1994-01-14 | Method of forming the multilayer wiring on the semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR94000605A KR970003732B1 (en) | 1994-01-14 | 1994-01-14 | Method of forming the multilayer wiring on the semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
KR950024306A KR950024306A (ko) | 1995-08-21 |
KR970003732B1 true KR970003732B1 (en) | 1997-03-21 |
Family
ID=19375658
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR94000605A KR970003732B1 (en) | 1994-01-14 | 1994-01-14 | Method of forming the multilayer wiring on the semiconductor device |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR970003732B1 (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100624461B1 (ko) * | 2005-02-25 | 2006-09-19 | 삼성전자주식회사 | 나노 와이어 및 그 제조 방법 |
-
1994
- 1994-01-14 KR KR94000605A patent/KR970003732B1/ko not_active IP Right Cessation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100624461B1 (ko) * | 2005-02-25 | 2006-09-19 | 삼성전자주식회사 | 나노 와이어 및 그 제조 방법 |
Also Published As
Publication number | Publication date |
---|---|
KR950024306A (ko) | 1995-08-21 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20090223 Year of fee payment: 13 |
|
LAPS | Lapse due to unpaid annual fee |