KR970000705B1 - Multi-level metalizing method of semiconductor device - Google Patents

Multi-level metalizing method of semiconductor device Download PDF

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Publication number
KR970000705B1
KR970000705B1 KR93010714A KR930010714A KR970000705B1 KR 970000705 B1 KR970000705 B1 KR 970000705B1 KR 93010714 A KR93010714 A KR 93010714A KR 930010714 A KR930010714 A KR 930010714A KR 970000705 B1 KR970000705 B1 KR 970000705B1
Authority
KR
South Korea
Prior art keywords
layer
semiconductor device
organic layer
metal wire
depositing
Prior art date
Application number
KR93010714A
Other languages
Korean (ko)
Other versions
KR950001952A (en
Inventor
Dae-Ill Park
Sang-Hoon Park
Original Assignee
Hyundai Electronics Ind
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hyundai Electronics Ind filed Critical Hyundai Electronics Ind
Priority to KR93010714A priority Critical patent/KR970000705B1/en
Publication of KR950001952A publication Critical patent/KR950001952A/en
Application granted granted Critical
Publication of KR970000705B1 publication Critical patent/KR970000705B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method for fabricating a multi-layer metal wire of semiconductor device is disclosed. The method for fabricating the multi-layer wire of semiconductor device comprises the steps of: a) forming a first metal wire(5') in contact with a junction layer(3') on a structure having the junction layer(3'), a predetermined lower layer and a interlayer insulating layer(4); b) depositing a first organic layer(11) and an oxide layer(12) in this order; c) forming a second organic layer(13) having a predetermined pattern to contact with a second metal wire(10'); d) forming a contact hole by etching the oxide layer(12) and the first organic layer(11) using the second organic layer(13) as a mask to expose the first metal wire(5'); e) depositing a second metal layer(10') and coating a third organic layer(14); f) performing a etch-back process to expose the second metal wire(10'); and g) depositing a third metal layer(15). Thereby, planarization characteristic is greatly improved due to the organic layer, resulting in improvement in the reliability of the semiconductor device.
KR93010714A 1993-06-12 1993-06-12 Multi-level metalizing method of semiconductor device KR970000705B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR93010714A KR970000705B1 (en) 1993-06-12 1993-06-12 Multi-level metalizing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR93010714A KR970000705B1 (en) 1993-06-12 1993-06-12 Multi-level metalizing method of semiconductor device

Publications (2)

Publication Number Publication Date
KR950001952A KR950001952A (en) 1995-01-04
KR970000705B1 true KR970000705B1 (en) 1997-01-18

Family

ID=19357307

Family Applications (1)

Application Number Title Priority Date Filing Date
KR93010714A KR970000705B1 (en) 1993-06-12 1993-06-12 Multi-level metalizing method of semiconductor device

Country Status (1)

Country Link
KR (1) KR970000705B1 (en)

Also Published As

Publication number Publication date
KR950001952A (en) 1995-01-04

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