KR960703274A - ELECTRICALLY AND THERMALLY ENHANCED PACKAGE USING A SEPARATE SILICON SUBSTRATE - Google Patents

ELECTRICALLY AND THERMALLY ENHANCED PACKAGE USING A SEPARATE SILICON SUBSTRATE Download PDF

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KR960703274A
KR960703274A KR1019950705862A KR19950705862A KR960703274A KR 960703274 A KR960703274 A KR 960703274A KR 1019950705862 A KR1019950705862 A KR 1019950705862A KR 19950705862 A KR19950705862 A KR 19950705862A KR 960703274 A KR960703274 A KR 960703274A
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South Korea
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integrated circuit
silicon substrate
circuit die
package
package assembly
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KR1019950705862A
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Korean (ko)
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리챠드 그루버
윌리엄 슈
상 에스. 리
죠지 후지모토
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토마스 씨, 토코스
브이엘에스아이 테크놀로지, 인코포레이티드
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Publication of KR960703274A publication Critical patent/KR960703274A/en

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Abstract

집적회로 팩키지 어셈블리는 집적회로 다이(32)가 고정된 분리 실리콘기판(34)을 포함한다. 분리 실리콘기판(34)은 집적회로 다이(32)를 위한 열 분산기로 사용된다. 집적회로 다이(32)가 고정된 분리 실리콘기판(34)은 성형된 팩키지체(80) 또는 공동형 팩키지체(120) 내로 팩키지된다. 성형된 팩키지체(80)의 경우, 팩키지체는 리드프레임(42), 집적회로 다이(32) 및, 집적회로 다이(32)가 고정된 분리 실리콘기판(34)주위에 성형된다. 성형된 팩키지체(80)의 경우, 리드프레임(42)은 분리 실리콘기판(34)에 부착된 내부단부에서 형성된 접착핑거를 가진다. 또는 리드프레임은 분리 실리콘기판(34)이 고정된 다이부착 패드(20)를 가진다. 공동형 팩키지(120)의 경우, 팩키지체는 내부에 형성된 공동에 인접하여 형성된 장착표면을 포함하며, 장착표면은 그 상면에 고정된 분리 실리콘기판(102)을 구비한다. 공동형 팩키지체(120)는 세라믹 물질 또는 다층 인쇄회로기판으로 형성된다. 하나 또는 그 이상의 삽입부 지역(122)은 리드 프레임(42) 또는 집적회로 다이(114)에서 나온 접속와이어(125,127)의 부착을 위하여 실리콘기판(102)의 상면에 형성된다.The integrated circuit package assembly includes a separate silicon substrate 34 to which the integrated circuit die 32 is fixed. Separation silicon substrate 34 is used as a heat spreader for integrated circuit die 32. The separated silicon substrate 34 to which the integrated circuit die 32 is fixed is packaged into the molded package 80 or the cavity package 120. In the case of the molded package 80, the package is molded around the lead frame 42, the integrated circuit die 32, and the separated silicon substrate 34 to which the integrated circuit die 32 is fixed. In the case of the molded package 80, the lead frame 42 has an adhesive finger formed at the inner end attached to the separation silicon substrate 34. Alternatively, the lead frame has a die attach pad 20 to which a separate silicon substrate 34 is fixed. In the case of the cavity type package 120, the package body includes a mounting surface formed adjacent to a cavity formed therein, and the mounting surface has a separate silicon substrate 102 fixed to the upper surface thereof. The cavity package body 120 is formed of a ceramic material or a multilayer printed circuit board. One or more insert regions 122 are formed on the top surface of the silicon substrate 102 for attachment of the connecting wires 125, 127 from the lead frame 42 or the integrated circuit die 114.

Description

분리 실리콘기판을 사용하여 전기적 열적으로 향상된 팩키지 (ELECTRICALLY AND THERMALLY ENHANCED PACKAGE USING A SEPARATE SILICON SUBSTRATE)ELECTRICALLY AND THERMALLY ENHANCED PACKAGE USING A SEPARATE SILICON SUBSTRATE

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제5도는 제4도의 어셈블리와 유사한 팩키지 어셈블리의 단면도로서, 하나 이상의 전도층에 삽입부 위에 형성된 것을 도시한 도면.FIG. 5 is a cross-sectional view of a package assembly similar to the assembly of FIG. 4, showing one or more conductive layers formed over the insert.

Claims (34)

집적회로 다이, 상면과 하면을 가지는 분리 실리콘기판 및, 상기 집적회로 다이와 함께 상기 분리 실리콘 기판에 고정된 상기 분리 실리콘기판을 포함하는 팩키지체로 구성되고, 상기 집적회로 다이는 상기 분리 실리콘기판의 상기 상면에 고정되며, 상기 분리 실리콘기판은 상기 집적회로 다이를 위한 열 분산기로 사용되는 것을 특징으로 하는 집적회로 팩키지 어셈블리.An integrated circuit die, a package comprising a separate silicon substrate having an upper surface and a lower surface, and a separate silicon substrate fixed to the separation silicon substrate together with the integrated circuit die, wherein the integrated circuit die is formed on the top surface of the separation silicon substrate. And the separation silicon substrate is used as a heat spreader for the integrated circuit die. 제1항에 있어서, 상기 집적회로 팩키지 어셈블리는, 리드프레임, 상기 집적회로 다이 및 상기 집적회로 다이가 고정된 상기 분리 실리콘기판 주변에 형성된 성형된 팩키지체인 상기 팩키지체와, 상기 리드프레임의 중심영역을 향해 안으로 연장되는 리드를 갖춘 상기 리드프레임을 포함하며, 상기 리드는 그 내부단부에서 형성된 접착핑거를 가지는 것을 특징으로 집적회로 팩키지 어셈블리.2. The integrated circuit package assembly of claim 1, wherein the integrated circuit package assembly is a molded package body formed around a separate silicon substrate to which a lead frame, the integrated circuit die, and the integrated circuit die are fixed, and a central region of the lead frame. And said leadframe having a lead extending inward toward said lead, said lead having an adhesive finger formed at an inner end thereof. 제2항에 있어서, 상기 집적회로 팩키지 어셈블리는 상기 분리 실리콘기판에 부착된 상기 접착핑거를 포함하는 것을 특징으로 하는 집적회로 팩키지 어셈블리.3. The integrated circuit package assembly of claim 2, wherein the integrated circuit package assembly includes the adhesive finger attached to the separation silicon substrate. 제3항에 있어서, 상기 리드프레임은 상기 분리 실리콘기판에 고정된 다이부착 패드부분을 가지는 것을 특징으로 하는 집적회로 팩키지 어셈블리.4. The integrated circuit package assembly of claim 3, wherein the leadframe has a die attach pad portion secured to the separation silicon substrate. 제2항에 있어서, 상기 분리 실리콘기판은 상기 집적회로 다이의 측면크기보다 큰 측면크기를 가지며, 적어도 하나의 삽입부지역은 상기 집적회로 다이 또는 상기 리드프레임에서 나온 접속와이어의 부착을 위해 상기 실리콘기판의 상기 상면에 형성되는 것을 특징으로 하는 집적회로 팩키지 어셈블리.3. The method of claim 2, wherein the separation silicon substrate has a side size larger than the side size of the integrated circuit die, and at least one insert region is attached to the silicon for attachment of a connection wire from the integrated circuit die or the leadframe. Integrated circuit package assembly, characterized in that formed on the upper surface of the substrate. 제5항에 있어서, 상기 분리 실리콘기판의 상기 상면에 형성된 상기 적어도 하나의 삽입부의 일부는 상기 실리콘기판의 상기 상면과 상기 집적회로 다이사이에서 연장되는 것을 특징으로 하는 집적회로 팩키지 어셈블리.6. The integrated circuit package assembly of claim 5, wherein a portion of the at least one insert formed on the upper surface of the separation silicon substrate extends between the upper surface of the silicon substrate and the integrated circuit die. 제5항에 있어서, 상기 실리콘기판의 상기 상면에 형성된 상기 적어도 하나의 삽입부의 일부는 상기 실리콘기판의 상기 상면과 상기 집적회로 다이의 하면사이에서 연장되어 다양한 크기의 집적회로 다이의 수용하는 것을 특징으로 하는 집적회로 팩키지 어셈블리.6. The integrated circuit die of claim 5, wherein a part of the at least one insert formed on the upper surface of the silicon substrate extends between the upper surface of the silicon substrate and the lower surface of the integrated circuit die. Integrated circuit package assembly. 제1항에 있어서, 상기 적어도 하나의 삽입부는 상기 실리콘기판의 상기 상면에 형성된 산화막의 층으로 형성되고, 상기 산화막의 층은 전도성 물질의 층으로 덮히는 것을 특징으로 하는 집적회로 팩키지 어셈블리.The integrated circuit package assembly of claim 1, wherein the at least one insert is formed of a layer of an oxide film formed on the upper surface of the silicon substrate, and the layer of the oxide film is covered with a layer of a conductive material. 제8항에 있어서, 상기 적어도 하나의 삽입부는 상기 실리콘기판의 상기 상면위에 형성된 산화막의 층으로 형성되고, 그 위에 산화막 및 전도성 물질로 구성된 다른 층이 형성되는 것을 특징으로 하는 집적회로 팩키지 어셈블리.10. The integrated circuit package assembly of claim 8, wherein the at least one insert is formed of a layer of an oxide film formed on the top surface of the silicon substrate, on which another layer of an oxide film and a conductive material is formed. 제1항에 있어서, 상기 팩키지체는 내부에 형성된 공동을 가지는 공동형 팩키지체이며, 상기 팩키지체는 상기 공동에 인접하여 형성된 장착표면을 포함하고, 상기 장착표면은 고정된 상기 분리 실리콘기판을 구비하는 것을 특징으로 하는 집적회로 팩키지 어셈블리.The method of claim 1, wherein the package is a cavity-type package having a cavity formed therein, the package includes a mounting surface formed adjacent to the cavity, the mounting surface has the fixed silicon substrate fixed Integrated circuit package assembly, characterized in that. 제10항에 있어서, 적어도 하나의 삽입부는 상기 공동형 팩키지체 또는 상기 집적회로 다이에서 나온 와이어의 접속을 위하여 상기 분리 실리콘기판의 상기 상면에 형성되는 것을 특징으로 집적회로 팩키지 어셈블리.11. The integrated circuit package assembly of claim 10, wherein at least one insert is formed on the top surface of the separation silicon substrate for connection of wires from the cavity package or the integrated circuit die. 제11항에 있어서, 상기 실리콘기판의 상기 상면에 형성된 상기 적어도 하나의 삽입부의 일부는 상기 실리콘기판의 상기 상면과 상기 집적회로 다이 사이에서 연장되어 여러 크기의 집적회로 다이를 수용하는 것을 특징으로 하는 집적회로 팩키지 어셈블리.12. The method of claim 11, wherein a portion of the at least one insert formed on the upper surface of the silicon substrate extends between the upper surface of the silicon substrate and the integrated circuit die to accommodate integrated circuit dies of various sizes. Integrated circuit package assembly. 제11항에 있어서, 상기 접속부는 와이어 접착 와이어인 것을 특징으로 하는 집적회로 팩키지 어셈블리.12. The integrated circuit package assembly of claim 11, wherein the connection portion is a wire bond wire. 제11항에 있어서, 상기 적어도 하나의 삽입부는 상기 실리콘기판의 상기 표면위에 형성된 산화막의 층으로 형성되고, 상기 산화막의 층은 전도성 물질의 층으로 덮히는 것을 특징으로 하는 집적회로 팩키지 어셈블리.12. The integrated circuit package assembly of claim 11, wherein the at least one insert is formed of a layer of oxide film formed on the surface of the silicon substrate, the layer of oxide film covered with a layer of conductive material. 제14항에 있어서, 상기 적어도 하나의 삽입부는 상기 실리콘기판의 상기 상면에 형성된 산화막의 층으로 형성되고, 그 위에 산화막 및 전도성 물질의 변형된 다른 충이 형성되는 것을 특징으로 하는 집적회로 팩키지 어셈블리.15. The integrated circuit package assembly of claim 14, wherein the at least one insert is formed of a layer of an oxide film formed on the top surface of the silicon substrate, on which a modified charge of the oxide film and conductive material is formed. 제14항에 있어서, 상기 팩키지체는 세라믹물질로 형성되는 것을 특징으로 하는 집적회로 팩키지 어셈블리.15. The integrated circuit package assembly of claim 14, wherein the package is formed of a ceramic material. 제14항에 있어서, 상기 팩키지체는 인쇄회로기판 구조로 형성되는 것을 특징으로 하는 집적회로 팩키지 어셈블리.15. The integrated circuit package assembly of claim 14, wherein the package body is formed of a printed circuit board structure. 집적회로 다이, 리드프레임 상면 및 하면을 가지는 분리 실리콘기판 및, 상기 집적회로 다이와 함께 장착된 상기 분리 실리콘기판을 포함하며, 리드프레임, 상기 집적회로 다이 및 상기 분리 실리콘기판 주변에서 형성되는 성형된 팩키지체로 구성되며, 상기 리드프레임은 상기 리드프레임의 중심영역을 향해 안으로 연장되는 리드를 가지고, 상기 리드는 그 내부단부에서 형성된 접착핑거를 가지며, 상기 집적회로 다이는 상기 분리 실리콘기판의 상기 상면에 장착되며, 상기 분리 실리콘기판은 상기 집적회로 다이를 위한 열 분산기로 사용되는 것을 특징으로 하는 집적회로 팩키지 어셈블리.A molded package comprising a separate silicon substrate having an integrated circuit die, a lead frame top and a bottom surface, and the separation silicon substrate mounted with the integrated circuit die, wherein the molded package is formed around the lead frame, the integrated circuit die and the separation silicon substrate. And a lead frame having a lead extending inward toward the center region of the lead frame, the lead having an adhesive finger formed at an inner end thereof, and the integrated circuit die mounted to the upper surface of the separation silicon substrate. Wherein said separate silicon substrate is used as a heat spreader for said integrated circuit die. 제18항에 있어서, 상기 분리 실리콘기판은 상기 집적회로 다이의 측면크기보다 큰 측면크기를 가지며, 적어도 하나의 삽입부지역은 상기 리드프레임 또는 상기 집적회로 다이에서 나온 접속와이어의 부착을 위한 상기 실리콘기판의 상기 상면에 형성되는 것을 특징으로 하는 집적회로 팩키지 어셈블리.19. The method of claim 18, wherein the separation silicon substrate has a side size greater than the side size of the integrated circuit die, and at least one insert region is the silicon for attachment of a connection wire from the leadframe or the integrated circuit die. Integrated circuit package assembly, characterized in that formed on the upper surface of the substrate. 제19항에 있어서, 상기 분리 실리콘기판의 상기 상면에 형성된 상기 적어도 하나의 삽입부의 일부는 상기 실리콘기판의 상기 상면과 상기 집적회로 다이 사이에서 연장되는 것을 특징으로 하는 집적회로 팩키지 어셈블리.20. The integrated circuit package assembly of claim 19, wherein a portion of the at least one insert formed on the top surface of the separation silicon substrate extends between the top surface of the silicon substrate and the integrated circuit die. 제19항에 있어서, 상기 적어도 하나의 삽입부는 상기 실리콘기판의 상기 표면에 형성된 산화막의 층으로 형성되고, 산화막의 층은 전도성 물질의 덮히는 것을 특징으로 하는 집적회로 팩키지 어셈블리.20. The integrated circuit package assembly of claim 19, wherein the at least one insert is formed of a layer of oxide film formed on the surface of the silicon substrate, the layer of oxide film being covered with a conductive material. 집적회로 다이, 상면과 하면을 가지는 분리 실리콘기판 및 내부에 공동을 구비한 팩키지체로 구성되고, 상기 집적회로 다이는 상기 분리 실리콘기판의 상기 상면에 고정되며, 상기 분리 실리콘기판은 상기 집적회로 다이를 위한 열 분산기로 사용되고, 상기 팩키지체는 상기 공동에 인접한 상기 팩키지체내에 형성된 장착표면을 가지며, 상기 장착표면은 장착된 상기 분리 실리콘기판을 가지는 것을 특징으로 하는 집적회로 팩키지 어셈블리.An integrated circuit die, a separate silicon substrate having an upper surface and a lower surface, and a package body having a cavity therein, wherein the integrated circuit die is fixed to the upper surface of the separation silicon substrate, and the separated silicon substrate is configured to Wherein said package has a mounting surface formed within said package adjacent said cavity, said mounting surface having said separate silicon substrate mounted thereon. 제22항에 있어서, 적어도 하나의 삽입부는 상기 공동형 팩키지체 또는 상기 집적회로 다이에서 나온 와이어의 절속을 위한 상기 실리콘기판의 상기 상면에 형성되는 것을 특징으로 하는 집적회로 팩키지 어셈블리.23. The integrated circuit package assembly of claim 22, wherein at least one insert is formed on the top surface of the silicon substrate for fastening wires from the cavity package or the integrated circuit die. 제23항에 있어서, 상기 실리콘기판의 상기 상면에 형성된 상기 적어도 하나의 삽입부의 일부는 상기 실리콘기판의 상기 상면과 상기 집적회로 다이 사이에서 연장되는 것을 특징으로 하는 집적회로 팩키기 어셈블리.24. The integrated circuit package assembly of claim 23, wherein a portion of the at least one insert formed on the top surface of the silicon substrate extends between the top surface of the silicon substrate and the integrated circuit die. 제23항에 있어서, 상기 적어도 하나의 삽입부는 상기 실리콘기판의 상기 상면에 형성된 산화막의 층으로 형성되고, 상기 산화막층은 전도성 물질의 층으로 덮히는 것을 특징으로 하는 집적회로 팩키지 어셈블리.24. The integrated circuit package assembly of claim 23, wherein the at least one insert is formed of a layer of an oxide film formed on the top surface of the silicon substrate, wherein the oxide layer is covered with a layer of conductive material. 제22항에 있어서, 상기 팩키지체는 세라믹물질로 형성되는 것을 특징으로 하는 집적회로 팩키지 어셈블리.23. The integrated circuit package assembly of claim 22, wherein the package body is formed of a ceramic material. 제22항에 있어서, 상기 팩키지체는 인쇄회로기판 구조로 형성되는 것을 특징으로 하는 집적회로 팩키지 어셈블리.23. The integrated circuit package assembly of claim 22, wherein the package body is formed of a printed circuit board structure. 집적회로 다이를 냉각하는 집적회로 다이 냉각방법으로서, 상면과 하면을 가지는 분리 실리콘기판의 상면에 상기 집적회로 다이를 고정시키는 고정단계, 집적회로 다이와 한께 팩키지체내에 상기 분리 실리콘기판에 고정된 상기 분리 실리콘기판을 팩키지하는 팩키지단계 및, 상기 분리 실리콘기판을 사용하여 상기 집적회로 다이에서 나온 열을 전도하는 전도단계로 구성되는 것을 특징으로 하는 집적회로 다이 냉각방법.An integrated circuit die cooling method for cooling an integrated circuit die, comprising: a fixing step of fixing the integrated circuit die to an upper surface of a separated silicon substrate having an upper surface and a lower surface, wherein the integrated silicon die is fixed to the separated silicon substrate in an integrated circuit die and a package. A package step of packaging a separated silicon substrate, and a conducting step of conducting heat from the integrated circuit die using the separated silicon substrate. 제28항에 있어서, 상기 집적회로 다이와 함께 팩키지체내에 상기 분리 실리콘기판에 고정된 상기 분리 실리콘기판을 팩키지하는 팩키지단계는 리드프레임, 상기 집적회로 다이 및 상기 집적회로 다이가 고정된 상기 분리 실리콘기판 주위에서 팩키지체를 성형하는 단계를 포함하는 것을 특징으로 하는 집적회로 다이 냉각방법.29. The package step of claim 28, wherein the package step of packaging the separation silicon substrate fixed to the separation silicon substrate in the package together with the integrated circuit die comprises: a lead frame, the integrated circuit die and the separation silicon substrate to which the integrated circuit die is fixed. Forming a package around the integrated circuit die cooling method. 제28항에 있어서, 상기 집적회로 다이와 함께 팩키지체내에 상기 분리 실리콘기판에 고정된 상기 분리 실리콘기판을 팩키지하는 팩키지단계는 상기 공동에 인접하여 형성된 장착표면에 공동형 팩키지에서의 공동을 제공하여 상기 장착표면에 상기 분리 실리콘기판을 고정하는 단계를 포함하는 것을 특징으로 하는 집적회로 다이 냉각방법.31. The package step of claim 28, wherein the package step of packaging the discrete silicon substrate secured to the discrete silicon substrate in a package with the integrated circuit die provides the cavity in a cavity package on a mounting surface formed adjacent to the cavity. And fixing said separation silicon substrate to a mounting surface. 제28항에 있어서, 상기 방법은 상기 집적회로 다이 또는 상기 리드프레임에서 상기 실리콘기판의 상기 상면에 형성된 적어도 하나의 삽입부지역까지 접속화이어를 부착하는 단계를 포함하는 것을 특징으로 하는 집적회로 다이 냉각방법.29. The integrated circuit die cooling of claim 28, wherein the method comprises attaching interconnect wires from the integrated circuit die or the leadframe to at least one insertion zone formed in the top surface of the silicon substrate. Way. 제28항에 있어서, 상기 방법은 상기 집적회로 다이 또는 상기 리드프레임에서 상기 실리콘기판의 상기 상면에 형성된 적어도 하나의 삽입부지역까지 접속와이어를 부착하는 단계를 포함하는 것을 특징으로 하는 집적회로 다이 냉각방법.29. The integrated circuit die cooling of claim 28, wherein the method comprises attaching connection wires from the integrated circuit die or leadframe to at least one insertion zone formed in the top surface of the silicon substrate. Way. 제32항에 있어서, 상기 집적회로 다이 또는 상기 리드프레임에서 상기 실리콘기판의 상기 상면에 형성된 적어도 하나의 삽입부지역까지 접속화이어를 부착하는 부착단계는 상기 실리콘기판의 상기 상면과 상기 집적회로 다이 사이에서 연장되는 적어도 하나의 삽입부에 접속와이어를 부착하는 단계를 포함하는 것을 특징으로 하는 집적회로 다이 냉각방법.33. The method of claim 32, wherein attaching a connection wire from the integrated circuit die or the lead frame to at least one insertion region formed on the top surface of the silicon substrate is performed between the top surface of the silicon substrate and the integrated circuit die. Attaching a connection wire to at least one insertion portion extending from the integrated circuit die cooling method. 제32항에 있어서, 상기 방법은 상기 실리콘기판의 상기 표면에 형성된 상기 산화막의 층위에 형성된 전도성 물질의 층에 상기 접속와이어를 부착하는 단계를 포함하는 것을 특징으로 하는 집적회로 다이 냉각방법.33. The method of claim 32, wherein the method comprises attaching the connection wire to a layer of conductive material formed on a layer of the oxide film formed on the surface of the silicon substrate. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950705862A 1993-06-23 1994-06-13 ELECTRICALLY AND THERMALLY ENHANCED PACKAGE USING A SEPARATE SILICON SUBSTRATE KR960703274A (en)

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US8212293A 1993-06-23 1993-06-23
US08/082122 1993-06-23
US16961793A 1993-12-17 1993-12-17
US08/169617 1993-12-17
PCT/US1994/006739 WO1995000973A1 (en) 1993-06-23 1994-06-13 Electrically and thermally enhanced package using a separate silicon substrate

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