KR960700525A - 기판에 반도체 칩을 본딩시키는 방법(method of bonding semiconductor chips to a substrate) - Google Patents

기판에 반도체 칩을 본딩시키는 방법(method of bonding semiconductor chips to a substrate)

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KR960700525A
KR960700525A KR1019950703111A KR19950703111A KR960700525A KR 960700525 A KR960700525 A KR 960700525A KR 1019950703111 A KR1019950703111 A KR 1019950703111A KR 19950703111 A KR19950703111 A KR 19950703111A KR 960700525 A KR960700525 A KR 960700525A
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pad
low temperature
aluminum
bond
aluminum alloy
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KR1019950703111A
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마이클 이. 토마스
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존 엠. 클락 3세
내쇼날 세미컨덕터 코포레이션
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Publication of KR960700525A publication Critical patent/KR960700525A/ko

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    • H—ELECTRICITY
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
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    • H01L2924/14—Integrated circuits

Abstract

캐리어상의 해당 패드에 반도체 칩상의 패드를 본딩시키는 방법에 있어서, 와이어 볼은 저온 용융 알루미늄합금 본드 와이어의 한 단부를 상기 칩 패드에 본딩시킴으로써 상기 칩상의 패드에 부착된다. 그리고 나서, 상기 와이어는 본드에서 절단된다. 미리 결정된 시간 주기 동안 상기 본드 와이어 재료의 융점보다 약간 높은 온도로 상기 볼은 가열함으로써 사기 칩 패드상에 구슬 형태가 형성된다. 그후, 용융된 구슬 형태는 상기 캐리어 상의 해당 패드와 접촉하게 배치된다.

Description

기판에 반도체 칩을 본딩시키는 방법(METHOD OF BONDING SEMICONDUCTOR CHIPS TO A SUBSTRATE)
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1a도 내지 제1d도는 본 발명의 바람직한 실시예에 따라 멀티 칩 캐리어에 반도체 칩을 본딩시키는 단계를 개략적으로 도시한 것이다.

Claims (14)

1)저온 용융 알루미늄 합금 재료를 포함하는 뵨드 와이어를 제공하는 단계, 2)반도체 칩상의 패드에 상기 본드 와이어의 한 단부를 본딩시킴으로써 상기 칩상의 패드에 부착된 와이어 볼을 형성하는 단계, 3)상기 본드에서 상기 와이어를 절단하는 단계, 4)미리 결정된 시간 주기 동안 상기 본드 와이어 재료의 융점보다 약간 높은 온도로 상기 볼을 가열함으로써 상기 칩 패드상에 구슬형태를 형성하는 단계, 및 5)캐리어상의 해당 패드와 접촉하게 용융된 구슬형태를 배치시키는 단계를 포함하는, 캐리어상의 해당 패드에 반도체 칩상의 패드를 본딩시키는 방법.
제1항에 있어서, 상기 저온 용융 알루미늄 합금 재료는 알루미늄-게르마늄 합금을 포함하는, 캐리어상의 해당 패드에 반도체 칩상의 패드를 본딩시키는 방법.
제1항에 있어서, 상기 저온 용융 알루미늄 합금 재료는 알루미늄-마그네슘 합금을 포함하는, 캐리어상의 해당 패드에 반도체 칩상의 패드를 본딩시키는 방법.
제1항에 있어서, 상기 저온 용융 알루미늄 합금 재료는 알루미늄-구리 합금을 포함하는, 캐리어 상의 해당 패드에 반도체 칩상의 패드를 본딩시키는 방법.
제1항에 있어서, 단계4) 및 단계5)는 환원 또는 불활성 상태하에서 이행되는, 캐리어상의 해당 패드에 반도체 칩상의 페드를 본딩시키는 방법.
1)가열된 캐필러리튜브로부터 반도체 칩상의 패드상에 저온 용융 알루미늄 합금을 포함하는 용융된 본딩재료의 볼을 분배함으로써 상기 칩상의 패드상에 구슬 형태를 형성하는 단계. 2)미리 결정된 시간 주기 동안 상기 본딩 재료의 융점 보다 약간 높은 온도로 상기 구슬 형태를 가열하는 단계, 및 3)캐리어상의 해당 패드와 접촉하게 상기 용융된 구슬 형태를 배치시키는 단계를 포함하는 캐리어 상의 해당 패드에 반도체 칩상의 패드를 본딩시키는 방법.
제6항에 있어서, 상기 저온 용융 알루미늄 합금은 알루미늄-게르마늄 합금을 포함하는 캐리어상의 해당패드에 반도체 칩상의 패드를 본딩시키는 방법.
제6항에 있어서, 상기 저온 용융 알루미늄 합금은 알루미늄-마그네슘 합금을 포함하는, 캐리어 상의 해당 패드에 반도체 칩상의 패드를 본딩시키는 방법.
제6항에 있어서, 상기 저온 용융 알루미늄 합금은 알루미늄-구리 합금을 포함하는, 캐리어상의 해당 패드에 반도체 칩상의 패드를 본딩시키는 방법.
제6항에 있어서, 단계2) 및 단계3)는 환원 또는 불활성 상태하에서 이행되는, 캐리어 상의 해당 패드에 반도체 칩상의 패드를 본딩시키는 방법.
1)반도체 칩상에 적어도 하나의 알루미늄 본드 패드를 형성하는 단계, 2)상기 적어도 하나의 본드 패드 및 상기 반도체 칩의 표면 상에 보호층을 형성하는 단계, 3)상기 알루미늄을 노출시키도록 각각의 알루미늄 패드에 대해 상기 보호층내에 윈도우를 형성하는 단계, 4)저온 용융 알루미늄 합금 재료를 포함하는 본드 와이어를 제공하는 단계, 5)상기 칩상의 패드에 상기 본드 와이어의 한 단부를 본딩시킴으로써 상기 칩상의 패드에 부착된 와이어 본드 볼을 형성하는 단계, 6)상기 본드에서 상기 본드 와이어를 절단하는 단계, 7)미리 결정된 시간 주기 동안 상기 본드 와이어 재료의 융점보다 약간 높은 온도로 상기 볼을 가열함으로써 상기 칩 패드상에 구슬 형태를 형성하는 단계, 및 8)캐리어상의 해당 패드와 접촉하게 상기 용융된 구슬 형태를 배치시키는 단계, 포함하는 캐리어상의 해당 패드에 반도체 칩상의 패드를 본딩시키는 방법.
제11항에 있어서, 상기 저온 용융 알루미늄 합금 재료는 알루미늄-마그네슘 합금을 포함하는, 캐리어상의 해당 패드에 반도체 칩상의 패드를 본딩시키는 방법.
제11항에 있어서, 상기 저온 용융 알루미늄합금 재료는 알루미늄-게르마늄 합금을 포함하는, 캐리어상의 해당 패드에 반도체 칩상의 패드를 본딩시키는 방법.
제11항에 있어서, 상기 저온 용융 알루미늄합금 재료는 알루미늄-구리 합금을 포함하는, 캐리어상의 해당 패드에 반도체 칩상의 패드를 본딩시키는 방법. 11항에 있어서, 단계7) 및 단계8)는 환원 또는 불활성 상태하에서 이행되는, 캐리어상의 해당 패드에 반도체 칩상의 패드를 본딩시키는 방법.
※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950703111A 1993-02-09 1994-02-28 기판에 반도체 칩을 본딩시키는 방법(method of bonding semiconductor chips to a substrate) KR960700525A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/015,473 1993-02-09
US08/015,473 US5249732A (en) 1993-02-09 1993-02-09 Method of bonding semiconductor chips to a substrate
PCT/US1994/001401 WO1994018699A1 (en) 1993-02-09 1994-02-08 Method of bonding semiconductor chips to a substrate

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KR960700525A true KR960700525A (ko) 1996-01-20

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Country Link
US (1) US5249732A (ko)
EP (1) EP0683922B1 (ko)
JP (1) JPH08506698A (ko)
KR (1) KR960700525A (ko)
DE (1) DE69418184T2 (ko)
WO (1) WO1994018699A1 (ko)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5665639A (en) * 1994-02-23 1997-09-09 Cypress Semiconductor Corp. Process for manufacturing a semiconductor device bump electrode using a rapid thermal anneal
US5537738A (en) * 1995-02-10 1996-07-23 Micron Display Technology Inc. Methods of mechanical and electrical substrate connection
US5612256A (en) * 1995-02-10 1997-03-18 Micron Display Technology, Inc. Multi-layer electrical interconnection structures and fabrication methods
US5766053A (en) * 1995-02-10 1998-06-16 Micron Technology, Inc. Internal plate flat-panel field emission display
DE19509262C2 (de) * 1995-03-15 2001-11-29 Siemens Ag Halbleiterbauelement mit Kunststoffumhüllung und Verfahren zu dessen Herstellung
US6001724A (en) * 1996-01-29 1999-12-14 Micron Technology, Inc. Method for forming bumps on a semiconductor die using applied voltage pulses to an aluminum wire
US5834062A (en) * 1996-06-27 1998-11-10 Motorola, Inc. Material transfer apparatus and method of using the same
US6174449B1 (en) 1998-05-14 2001-01-16 Micron Technology, Inc. Magnetically patterned etch mask
US5897341A (en) * 1998-07-02 1999-04-27 Fujitsu Limited Diffusion bonded interconnect
US6234376B1 (en) * 1999-07-13 2001-05-22 Kulicke & Soffa Investments, Inc. Supplying a cover gas for wire ball bonding
KR100591461B1 (ko) * 2005-03-04 2006-06-20 (주)실리콘화일 두 반도체 기판의 알루미늄 전극 접합방법
US7442570B2 (en) 2005-03-18 2008-10-28 Invensence Inc. Method of fabrication of a AL/GE bonding in a wafer packaging environment and a product produced therefrom
US8567246B2 (en) 2010-10-12 2013-10-29 Invensense, Inc. Integrated MEMS device and method of use
US8947081B2 (en) 2011-01-11 2015-02-03 Invensense, Inc. Micromachined resonant magnetic field sensors
US9664750B2 (en) 2011-01-11 2017-05-30 Invensense, Inc. In-plane sensing Lorentz force magnetometer
US8860409B2 (en) 2011-01-11 2014-10-14 Invensense, Inc. Micromachined resonant magnetic field sensors
WO2016130722A1 (en) 2015-02-11 2016-08-18 Invensense, Inc. 3D INTEGRATION USING Al-Ge EUTECTIC BOND INTERCONNECT
CN105016291A (zh) * 2015-06-07 2015-11-04 上海华虹宏力半导体制造有限公司 可减少mems键合过程中铝锗键合桥连的结构
US10192850B1 (en) 2016-09-19 2019-01-29 Sitime Corporation Bonding process with inhibited oxide formation

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60140849A (ja) * 1983-12-28 1985-07-25 Fujitsu Ltd ゲルマニウム半導体装置
JPS6293335A (ja) * 1985-10-18 1987-04-28 Sumitomo Electric Ind Ltd 半導体装置の結線用導体
US5014111A (en) * 1987-12-08 1991-05-07 Matsushita Electric Industrial Co., Ltd. Electrical contact bump and a package provided with the same
JP2891432B2 (ja) * 1989-12-27 1999-05-17 田中電子工業株式会社 半導体材料の接続方法，それに用いる接続材料及び半導体装置
JPH03208354A (ja) * 1990-01-10 1991-09-11 Mitsubishi Electric Corp 半導体装置およびその製造方法
JPH0437138A (ja) * 1990-06-01 1992-02-07 Mitsubishi Materials Corp ワイヤーバンプによるバンプ形成方法
US5193738A (en) * 1992-09-18 1993-03-16 Microfab Technologies, Inc. Methods and apparatus for soldering without using flux

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JPH08506698A (ja) 1996-07-16
US5249732A (en) 1993-10-05
EP0683922B1 (en) 1999-04-28
WO1994018699A1 (en) 1994-08-18
DE69418184T2 (de) 1999-12-02
DE69418184D1 (de) 1999-06-02
EP0683922A1 (en) 1995-11-29

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