KR960043274A - High breakdown voltage MOS transistor and its manufacturing method - Google Patents

High breakdown voltage MOS transistor and its manufacturing method Download PDF

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KR960043274A
KR960043274A KR1019950014243A KR19950014243A KR960043274A KR 960043274 A KR960043274 A KR 960043274A KR 1019950014243 A KR1019950014243 A KR 1019950014243A KR 19950014243 A KR19950014243 A KR 19950014243A KR 960043274 A KR960043274 A KR 960043274A
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layer
forming
mos transistor
substrate
refractory metal
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KR1019950014243A
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KR100200343B1 (en
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이대영
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김광호
삼성전자 주식회사
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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32051—Deposition of metallic or metal-silicide layers
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

본 발명은 고내압 모스 트랜지스터에 관한 것으로서, 더욱 상세하게는, 게이트 전극 아래 부분이 기판 표면보다 낮게 위치하도록 형성하는 모스 트랜지스터 및 그 제조 방법에 관한 것이다. 본 발명은, 제1도전형의 반도체 기판에 제2도전형의 불순물을 주입하여 이온 주입층을 형성하고, 이온 주입층의 상부에 산화규소를 적층한 후 일정 부분만을 남기고 식각하여 산화막을 형성하고, 내화성 금속을 적층하고 열처리하여 실리사이드막을 형성하고, 남은 내화성 금속 및 산화막을 제거하고, 산화규소, 질화규소, 산화규소를 차례로 적층한 다음 실리사이드막의 위 부분만을 남기고 식각하여 개구부를 가진 삼중층을 형성하고, 개구부의 측면에 절연 물질로 측벽을 형성하고, 두 측벽의 사이에 드러나 있는 기판을 상기 이온 주입층보다 깊게 식각하여 오목부를 형성함과 동시에 이온 주입층을 소스 영역 및 드레인 영역으로 분리시키고, 오목부에 산화 물질로 게이트 산화막을 형성하고, 게이트 산화막 위에 도전 물질로 게이트 전극을 형성한 다음, 소스 및 드레인 영역과 각각 연결되는 소스 및 드레인 전극을 도전 물질로 형성하는 공정을 포함한다. 이 발명에서는 게이트 전극의 하부가 기판의 안쪽으로 들어가 있어, 소스 영역과 드레인 영역의 공핍층이 같은 평면 상에 놓이지 않는다. 이 때문에 드레인 영역에 고전압이 인가된다 하더라도 종래의 모스 트랜지스터보다 펀치 스루 형상을 억제할 수 있고 항복 전압이 높아지므로, 채널의 길이가 줄어들어도 높은 내압을 유지할 수 있다. 또, 오목부의 하부에 형성되어 있는 고농도의 웰은 공핍층이 옆으로 뻗어 확대되는 것을 억제하는 펀치 스루 항복을 막아줌과 동시에, 종래의 채널 문턱 조절(channel threshold adjust)의 역할을 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high breakdown voltage MOS transistor, and more particularly, to a MOS transistor in which a portion under the gate electrode is positioned lower than a substrate surface, and a method of manufacturing the same. According to the present invention, an ion implantation layer is formed by implanting impurities of a second conductivity type into a semiconductor substrate of the first conductivity type, and after the silicon oxide is deposited on the upper portion of the ion implantation layer, the oxide film is formed by etching leaving only a certain portion. To form a silicide film by laminating and heat-treating a refractory metal, removing the remaining refractory metal and oxide film, laminating silicon oxide, silicon nitride, and silicon oxide in turn, and then etching, leaving only the upper part of the silicide film and etching to form a triple layer having an opening. A sidewall is formed of an insulating material on the side of the opening, and the substrate exposed between the two sidewalls is etched deeper than the ion implantation layer to form a recess, and the ion implantation layer is separated into a source region and a drain region. A gate oxide film is formed of an oxide material in the portion, and a gate electrode is formed of a conductive material over the gate oxide film. Um, and a step of forming the source and drain electrodes respectively connected with source and drain regions with a conductive material. In the present invention, the lower portion of the gate electrode enters the inside of the substrate so that the depletion layers of the source region and the drain region do not lie on the same plane. For this reason, even if a high voltage is applied to the drain region, the punch-through shape can be suppressed and the breakdown voltage is higher than that of the conventional MOS transistor, so that a high breakdown voltage can be maintained even if the channel length is reduced. In addition, a well-concentrated well formed in the lower portion of the concave portion prevents punch-through breakdown that prevents the depletion layer from extending sideways and at the same time serves as a conventional channel threshold adjust.

Description

고내압 모스 트랜지스터 및 그 제조 방법High breakdown voltage MOS transistor and its manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명의 실시예에 따른 모스 트랜지스터의 구조를 도시한 단면도이다.2 is a cross-sectional view showing the structure of a MOS transistor according to an embodiment of the present invention.

Claims (18)

서로 분리되어 있는 제2도전형의 제1 및 제2영역이 형성되어 있고, 상기 제1 및 제2영역 사이의 상기 기판 표면은 상기 제1 및 제2영역의 깊이 이상으로 오목하게 패인 오목부를 가지고 있는 제1도전형의 반도체 기판, 상기 기판의 상기 오목부 위에 형성되어 있는 게이트 산화막, 상기 기판의 상기 제1 및 제2영역 위에 형성되어 있으며 절연 물질로 이루어져 있는 절연층, 상기 게이트 산화막 위에 형성되어 있으며 상기 제1 및 제2영역과 절연되어 있는 게이트 전극, 그리고 상기 제1 및 제2영역과 각각 연결되어 있는 제1 및 제2전극을 포함하고 있는 고내압 모스 트랜지스터.First and second regions of the second conductive type separated from each other are formed, and the substrate surface between the first and second regions has recesses recessed concave beyond the depths of the first and second regions. A first conductive semiconductor substrate, a gate oxide film formed on the concave portion of the substrate, an insulating layer formed on the first and second regions of the substrate and made of an insulating material, and formed on the gate oxide film And a gate electrode insulated from the first and second regions, and first and second electrodes connected to the first and second regions, respectively. 제1항에서, 상기 절연층은 산화규소, 질화규소, 산화규로로 각각 이루어진 제1산화층, 질화층, 제2산화층의 삼중층으로 이루어져 있는 고내압 모스 트랜지스터.The high voltage resistance MOS transistor of claim 1, wherein the insulation layer comprises triple layers of a first oxide layer, a nitride layer, and a second oxide layer each of silicon oxide, silicon nitride, and silicon oxide. 제1항 또는 제2항에서, 상기 제1 및 제2영역과 상기 절연층의 사이에 형성되어 있으며 내화성 금속과 규소의 화합물인 실리사이드층을 더 포함하는 고내압 모스 트랜지스터.The high voltage resistance MOS transistor according to claim 1 or 2, further comprising a silicide layer formed between the first and second regions and the insulating layer, wherein the silicide layer is a compound of a refractory metal and silicon. 제3항에서, 상기 내화성 금속은 텅스텐 또는 티타늄인 고내압 모스 트랜지스터.The high breakdown voltage MOS transistor of claim 3, wherein the refractory metal is tungsten or titanium. 제3항에서, 상기 실리사이드층은 상기 게이트 산화막과 떨어져 있으며, 상기 게이트 산화막과 상기 실리사이드층 사이의 상기 제1 및 제2영역 상부와 상기 절연층의 측면에 형성되어 있으며 절연 물질로 이루어져 있어 상기 게이트 전극과 상기 제1 및 제2영역을 절연하는 측벽을 더 포함하는 고내압 모스 트랜지스터.4. The gate of claim 3, wherein the silicide layer is separated from the gate oxide layer, is formed on an upper surface of the first and second regions between the gate oxide layer and the silicide layer and a side surface of the insulating layer, and is formed of an insulating material. The high breakdown voltage MOS transistor further comprises a sidewall insulating the electrode and the first and second regions. 제1항에서, 상기 기판은 상기 기판의 오목부의 아래에 형성되어 있으며 상기 기판보다 고농도인 제1도전형의 제3영역을 더 포함하는 고내압 모스 트랜지스터.The MOS transistor of claim 1, wherein the substrate further includes a third region of a first conductivity type formed under a recess of the substrate and having a higher concentration than that of the substrate. 제1도전형의 반도체 기판에 제2도전형의 불순물을 주입하여 이온 주입층을 형성하는 제1공정, 상기 이온주입층의 상부에 개구부를 가지는 절연층을 형성하는 제2공정, 상기 개구부의 바닥을 상기 이온 주입층보다 깊게 식각하여 상기 이온 주입층을 소스 영역 및 드레인 영역으로 분리시키는 제3공정, 상기 절연층에 의하여 덮이지 않은 상기 기판 표면에 산화 물질로 게이트 산화막을 형성하는 제4공정, 상기 게이트 산화막 위에 도전 물질로 게이트 전극을 형성하는 제5공정, 그리고 상기 소스 및 드레인 영역과 각각 연결되는 소스 및 드레인 전극을 도전물질로 형성하는 제6공정을 포함하는 고내압 모스 트랜지스터의 제조 방법.A first step of forming an ion implantation layer by injecting impurities of a second conductivity type into a semiconductor substrate of a first conductivity type, a second step of forming an insulating layer having an opening in an upper portion of the ion implantation layer, and a bottom of the opening Etching deeper than the ion implantation layer to separate the ion implantation layer into a source region and a drain region, a fourth process of forming a gate oxide film with an oxidized material on the surface of the substrate not covered by the insulating layer, And a fifth step of forming a gate electrode with a conductive material on the gate oxide film, and a sixth step of forming a source and a drain electrode connected to the source and drain regions, respectively, with a conductive material. 제7항에서, 상기 제1공정과 제2공정 사이에, 상기 개구부가 형성될 부분을 제외한 상기 이온 주입층의 상부를 실리사이드화하는 공정을 더 포함하는 고내압 모스 트랜지스터의 제조 방법.8. The method of claim 7, further comprising silicifying an upper portion of the ion implantation layer between the first process and the second process except for the portion where the opening is to be formed. 제8항에서, 상기 실리사이드화 공정은, 상기 개구부가 형성될 부분에 절연막을 형성하는 공정, 내화성 금속을 적충하고 열처리하여 실리사이드막을 형성하는 공정, 그리고 상기 내화성 금속 및 절연막을 제거하는 공정을 포함하는 고내압 모스 트랜지스터 제조방법.The method of claim 8, wherein the silicide forming process includes forming an insulating film in a portion where the opening is to be formed, forming a silicide film by loading and heat treating a refractory metal, and removing the refractory metal and the insulating film. Method for manufacturing high breakdown voltage MOS transistor. 제9항에서, 상기 내화성 금속은 텅스텐 또는 티타늄인 고내압 모스 트랜지스터의 제조방법.The method of claim 9, wherein the refractory metal is tungsten or titanium. 제9항 또는 제10항에 있어서, 상기 내화성 금속을 열처리할 때에는 800℃정도의 온도에서 질소 분위기로 약 30분 정도 열처리하는 고내압 모스 트랜지스터의 제조 방법.The method of manufacturing a high breakdown voltage MOS transistor according to claim 9 or 10, wherein the heat-resistant metal is heat-treated for about 30 minutes in a nitrogen atmosphere at a temperature of about 800 ° C. 제9항에서, 상기 내화성 금속의 제거 공정에서는 HF용액을 이용하는 고내압 모스 트랜지스터의 제조방법.The method of claim 9, wherein in the removing of the refractory metal, an HF solution is used. 제7항에서, 상기 절연층은 산화층, 질화층, 산화층의 삼중층으로 형성하는 고내압 모스 트랜지스터의 제조 방법.The method of claim 7, wherein the insulating layer is formed of a triple layer of an oxide layer, a nitride layer, and an oxide layer. 제7항에서, 상기 제3공정과 제4공정의 사이에, 제1도전형의 불순물을 주입하여 상기 기판에 비하여 고농도인 웰을 형성하는 공정을 더 포함하는 고내압 모스 트랜지스터의 제조 방법.The method of claim 7, further comprising forming a well having a higher concentration than that of the substrate by injecting impurities of a first conductivity type between the third process and the fourth process. 제1도전형의 반도체 기판에 제2도전형의 불순물을 주입하여 이온 주입층을 형성하는 공정, 상기 이온 주입층의 상부에 산화규소를 적층한 후 일정 부분만 남기고 식각하여 산화막을 형성하는 공정, 내화성 금속을 적층하고 열처리하여 실리사이드막을 형성하는 공정, 상기 내화성 금속 및 산화막을 제거하는 공정, 산화규소, 질화규소, 산화규소를 차례로 적층한 다음 상기 실리사이드막의 위부분만을 남기고 식각하여 개구부를 가진 삼중층을 형성하는 공정, 상기 개구부의 측면에 절연 물질로 측벽을 형성하는 공정, 두 측벽의 사이에 드러나 있는 기판을 상기 이온 주입층보다 깊게 식각하여 오목부를 형성함과 동시에 상기 이온 주입층을 소스 영역 및 드레인 영역으로 분리시키는 공정, 상기 오목부에 산화물질로 게이트 산화막을 형성하는 공정, 상기 게이트 산화막 위에 도전 물질로 게이트 전극을 형성하는 공정, 그리고 상기 소스 및 드레인 영역과 각각 연결되는 소스 및 드레인 전극을 도전물질로 형성하는 공정을 포함하는 고내압 모스 트랜지스터의 제조방법.Implanting impurities of the second conductivity type into the semiconductor substrate of the first conductivity type, forming an ion implantation layer, stacking silicon oxide on the upper portion of the ion implantation layer, and etching to leave only a portion of the semiconductor layer; Stacking and heat-treating the refractory metal to form a silicide film, removing the refractory metal and the oxide film, stacking silicon oxide, silicon nitride, and silicon oxide, and then etching, leaving only the upper portion of the silicide film and etching. Forming a sidewall with an insulating material on a side surface of the opening; etching a substrate exposed between the two sidewalls deeper than the ion implantation layer to form a recess, and simultaneously forming a source region and a drain Separating into regions, forming a gate oxide film with an oxide material in the concave portion, and Forming a gate electrode with a conductive material on the gate oxide film, and a method for manufacturing a high-breakdown-voltage MOS transistor comprising the step of forming the source and drain electrodes are respectively connected to the source and drain regions with a conductive material. 제15항에서, 상기 내화성 금속은 텅스텐 또는 티타늄인 고내압 모스 트랜지스터의 제조방법.The method of claim 15, wherein the refractory metal is tungsten or titanium. 제15항 또는 제26항에서, 상기 내화성 금속을 열처리할 때에는 800℃ 정도의 온도에서 질소 분위기로 약 30분 정도 열처리하는 고내압 모스 트랜지스터의 제조방법.27. The method of claim 15 or 26, wherein when heat-treating the refractory metal, heat treatment is performed for about 30 minutes in a nitrogen atmosphere at a temperature of about 800 ° C. 제15항에서, 상기 내화성 금속의 제거 공정에서 HF용액을 이용하는 고내압 모스 트랜지스터의 제조방법.The method of manufacturing a high breakdown voltage MOS transistor according to claim 15, wherein HF solution is used in the step of removing the refractory metal. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
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