KR960043161A - BiCMOS device and its manufacturing method - Google Patents

Abstract

A bi CMOS device and its manufacturing method are described.

The second and fourth impurity regions are surrounded by the first impurity region, and the third impurity regions formed above and below the fourth impurity region are surrounded by the second impurity region in a ring shape, and the third and fourth impurity regions The edge of the second impurity region is in contact with.

Therefore, the number of photolithography processes for forming the impurity buried layers can be reduced, and the concentration of the buried layers can be adjusted relatively freely while greatly reducing the thermal processing time.

Description

BiCMOS device and its manufacturing method

As this is a public information case, the full text was not included.

4A to 4D are cross-sectional views illustrating a method of manufacturing the bi CMOS device of FIG. 3.

Claims (9)

The second and fourth impurity regions are surrounded by the first impurity region, and the third impurity regions formed above and below the fourth impurity region are surrounded by the second impurity region in a ring shape, and the third light fourth A bi CMOS device, wherein an edge of an impurity region and a second impurity region are in contact with each other. 2. The bi CMOS device according to claim 1, wherein the first and third impurity regions are of a first conductivity type, and the second and fourth impurity regions are of a second conductivity type. The bi-MOS device of claim 1, wherein the first impurity region is electrically insulated from the third impurity region. First step of forming a first impurity region by implanting impurity ions of a first conductivity type into a semiconductor substrate: Second process of forming an oxide film on a semiconductor substrate of the first impurity region: A second conductive type on the semiconductor substrate A third step of forming a second impurity region having a shape surrounded by the first impurity region by implanting impurity ions at a high concentration: a fourth step of removing the oxide film: a third and fourth impurity regions are formed on a semiconductor substrate A fifth process of forming a photoresist pattern having a shape of exposing a semiconductor substrate of a portion to be formed; and a fourth process of continuously implanting impurity ions of a first and a second conductivity type into the semiconductor substrate and surrounding the second impurity region; And a sixth step of forming a third impurity region above and below the impurity region and the fourth impurity region. The method of claim 4, wherein the impurity ions implanted in the sixth step have different diffusion coefficients. The method of claim 5, wherein the diffusion coefficient of the impurity implanted to form the third impurity region is larger than the diffusion coefficient of the impurity implanted to form the fourth impurity region. Way. 6. The method of claim 5, wherein the sixth step comprises: arsenic (As) ions having energy of 180KeV, dose of 5.0 × 10 ¹³ atoms / cm 2, boron (B) ion of 80KeV, and 2.0 × 10 ^13. A method of manufacturing a bi-MOS device, characterized in that it proceeds by continuously injecting in a dose amount of atoms / cm 2. 5. The method of claim 4, further comprising, after forming the silicon layer on the first, second, third, and fourth impurity regions after the sixth process, diffusing and activating the impurities. Method for producing a bi CMOS device. The method of manufacturing a bi-MOS device according to claim 8, wherein the silicon layer formed on the impurity region is a single crystal or polycrystalline silicon layer. ※ Note: The disclosure is based on the initial application.