KR960042910A - Semiconductor Device Formation Method - Google Patents

Semiconductor Device Formation Method Download PDF

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Publication number
KR960042910A
KR960042910A KR1019950010734A KR19950010734A KR960042910A KR 960042910 A KR960042910 A KR 960042910A KR 1019950010734 A KR1019950010734 A KR 1019950010734A KR 19950010734 A KR19950010734 A KR 19950010734A KR 960042910 A KR960042910 A KR 960042910A
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KR
South Korea
Prior art keywords
wafer
alignment mark
semiconductor device
forming
pedestal
Prior art date
Application number
KR1019950010734A
Other languages
Korean (ko)
Inventor
박기엽
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950010734A priority Critical patent/KR960042910A/en
Publication of KR960042910A publication Critical patent/KR960042910A/en

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Abstract

본 발명은 반도체소자 형성방법에 관한 것으로, 하부에 중첩정렬마크가 형성된 완전한 구형의 웨이퍼를 상기 웨이퍼보다 작게 형성된 웨이퍼 받침대 상부에 상기 중첩정렬마크가 노출되도록 형성하고 상기 웨이퍼 받침대 하부에 중첩정렬마크 판독기를 형성한 다음, 이를 이용한 후공정으로 반도체소자를 형성함으로써 반도체소자의 신뢰성을 향상시키고 반도체소자의 수율을 향상시킬 수 있는 기술이다.The present invention relates to a method of forming a semiconductor device, wherein a completely spherical wafer having an overlapping alignment mark formed at a lower portion thereof is formed to expose the overlapping alignment mark at an upper portion of a wafer pedestal formed smaller than the wafer, and an overlapping alignment mark reader under the wafer pedestal. After the formation of the semiconductor device, the semiconductor device is formed in a subsequent process using the same, thereby improving the reliability of the semiconductor device and improving the yield of the semiconductor device.

Description

반도체소자 형성방법Semiconductor Device Formation Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1A도 및 제1B도는 본 발명의 실시예에 따른 반도체소자 형성방법을 도시한 개략도.1A and 1B are schematic diagrams showing a method of forming a semiconductor device in accordance with an embodiment of the present invention.

Claims (7)

반도체소자 형성방법에 있어서, 플랫존이 없는 원형으로 하부에 중첩정렬마크가 형성된 웨이퍼를 형성하는 공정과, 상기 웨이퍼가 놓인 웨이퍼 받침대 하부에 중첩정렬마크 판독기를 설치하는 공정과 상기 웨이퍼 상부에 기판을 형성하는 공정을 포함하는 반도체소자 형성방법.A method of forming a semiconductor device, the method comprising: forming a wafer having a superimposed alignment mark at a lower portion in a circle without a flat zone, installing a superimposed alignment mark reader under a wafer pedestal on which the wafer is placed, and placing a substrate on the wafer. A semiconductor device forming method comprising the step of forming. 제1항에 있어서, 상기 중첩정렬마크는 광학적 또는 비광학적으로 측정할 수 있는 구조와 크기로 형성되는 것을 특징으로 하는 반도체소자 형성방법.The method of claim 1, wherein the overlap alignment mark is formed in a structure and size that can be measured optically or non-optically. 제1항에 있어서, 상기 중첩정렬마크는 상기 웨이퍼에 막을 형성하고 정렬마크 마스크를 이용한 식각공정을 실시함으로써 형성되는 것을 특징으로 하는 반도체소자 형성방법.The method of claim 1, wherein the overlap alignment mark is formed by forming a film on the wafer and performing an etching process using an alignment mark mask. 제1항 또는 제3항에 있어서, 상기 중첩정렬마크는 정렬마크 마스크를 이용하여 상기 웨이퍼를 식각함으로써 형성되는 것을 특징으로 하는 반도체소자 형성방법.The method of claim 1, wherein the overlap alignment mark is formed by etching the wafer using an alignment mark mask. 제1항에 있어서, 상기 웨이퍼의 받침대는 상기 웨이퍼보다 작은 크기로 형성되는 것을 특징으로 하는 반도체소자 형성방법.The method of claim 1, wherein the pedestal of the wafer is smaller than the wafer. 제1항에 있어서, 상기 중첩정렬마크 판독기는 상기 웨이퍼 상부에 설치되고 상기 웨이퍼 받침대 하부에 거울이 구비되는 것을 특징으로 하는 반도체소자 형성방법.The method of claim 1, wherein the overlap alignment mark reader is disposed on the wafer and a mirror is provided below the wafer pedestal. 원형의 실리콘 단결정을 스라이싱하여 웨이퍼를 형성하는 공정과, 상기 웨이퍼 하부에 중첩정렬마크를 형성하는 공정과, 상기 웨이퍼의 외곽을 그라인딩하고 후공정실시하는 반도체소자 형성방법.A method of forming a wafer by slicing a circular silicon single crystal, forming a superimposed alignment mark on the lower part of the wafer, and grinding the outer edge of the wafer and performing a post-process. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950010734A 1995-05-02 1995-05-02 Semiconductor Device Formation Method KR960042910A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950010734A KR960042910A (en) 1995-05-02 1995-05-02 Semiconductor Device Formation Method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950010734A KR960042910A (en) 1995-05-02 1995-05-02 Semiconductor Device Formation Method

Publications (1)

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KR960042910A true KR960042910A (en) 1996-12-21

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KR1019950010734A KR960042910A (en) 1995-05-02 1995-05-02 Semiconductor Device Formation Method

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170139263A (en) * 2016-06-09 2017-12-19 주식회사 디비하이텍 Wafer with align key and method of fabricating the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170139263A (en) * 2016-06-09 2017-12-19 주식회사 디비하이텍 Wafer with align key and method of fabricating the same

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